专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07521776B2 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers 有权
标题翻译：使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低
公开(公告)号：US07521776B2
公开(公告)日：2009-04-21
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger, III , Jack A. Mandelman , William Tonti
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

82. 发明申请

US20050167740A1 Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage 有权
标题翻译：掺杂半导体纳米管的垂直场效应晶体管在间隔物界定的通道中生长
公开(公告)号：US20050167740A1
公开(公告)日：2005-08-04
申请号：US10767039
申请日：2004-01-29
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/78 , H01L27/28 , H01L51/30 , H01L27/108
CPC分类号： H01L27/283 , B82Y10/00 , H01L51/0048 , H01L51/057 , Y10S977/70 , Y10S977/707 , Y10S977/721 , Y10S977/724
摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
摘要翻译：具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。可以在远离通道的口的间隔件的基部中设置间隙。通过间隙流过催化剂垫的反应物参与纳米管生长。

83. 发明申请

US20070108473A1 SEMICONDUCTOR OPTICAL SENSORS 有权
标题翻译：半导体光传感器
公开(公告)号：US20070108473A1
公开(公告)日：2007-05-17
申请号：US11164217
申请日：2005-11-15
申请人： Toshiharu Furukawa , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L31/101 , H01L27/14647 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： An optical sensor and method for forming the same. The optical sensor structure includes (a) a semiconductor substrate, (b) first, second, third, fourth, fifth, and sixth electrodes and (c) first, second, and third semiconducting regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes are at a second depth. The third and sixth electrodes are at a third depth. The first depth is greater than the second depth, and the second depth is greater than the third depth. The first, second, and third semiconducting regions are disposed between and in contact with the first and fourth electrodes, second and fifth electrodes, and third and sixth electrodes, respectively. The first, second, and third semiconducting regions are in contact with each other.
摘要翻译：一种光学传感器及其形成方法。光学传感器结构包括（a）半导体衬底，（b）第一，第二，第三，第四，第五和第六电极以及（c）第一，第二和第三半导电区域。第一和第四电极处于第一深度。第二和第五电极处于第二深度。第三和第六电极处于第三深度。第一深度大于第二深度，第二深度大于第三深度。第一，第二和第三半导体区域分别设置在第一和第四电极，第二和第五电极以及第三和第六电极之间并与之接触。第一，第二和第三半导电区域彼此接触。

84. 发明申请

US20060186416A1 MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
标题翻译：多层和晶体平面取向半导体基板
公开(公告)号：US20060186416A1
公开(公告)日：2006-08-24
申请号：US10906557
申请日：2005-02-24
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

85. 发明申请

US20060157743A1 Borderless contact structures 失效
标题翻译：无边界接触结构
公开(公告)号：US20060157743A1
公开(公告)日：2006-07-20
申请号：US11375624
申请日：2006-03-14
申请人： Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/11 , H01L27/1104
摘要： A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon line and a corresponding portion of the insulating sidewall layer in a contact region of the polysilicon line; and (e) forming a silicide layer on the sidewall of the polysilicon line in the contact region. Also an SRAM cell using the borderless contact structure and a method of fabricating the SRAM cell.
摘要翻译：一种无边界接触结构和制造该结构的方法，所述方法包括：（a）提供基底; （b）在所述衬底上形成多晶硅线，所述多晶硅线具有侧壁; （c）在多晶硅线路的侧壁上形成绝缘侧壁层; （d）在所述多晶硅线的接触区域中去除所述多晶硅线的一部分和所述绝缘侧壁层的相应部分; 和（e）在接触区域中的多晶硅线路的侧壁上形成硅化物层。也是使用无边界接触结构的SRAM单元和制造SRAM单元的方法。

86. 发明申请

US20050266627A1 Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage 失效
公开(公告)号：US20050266627A1
公开(公告)日：2005-12-01
申请号：US11180415
申请日：2005-07-13
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/78 , H01L27/28 , H01L51/30 , H01L21/336
CPC分类号： H01L27/283 , B82Y10/00 , H01L51/0048 , H01L51/057 , Y10S977/70 , Y10S977/707 , Y10S977/721 , Y10S977/724
摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

87. 发明申请

US20080116529A1 SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于半导体器件中的屏蔽带电充电的低温隔离结构
公开(公告)号：US20080116529A1
公开(公告)日：2008-05-22
申请号：US12022202
申请日：2008-01-30
申请人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/7833
摘要： A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.
摘要翻译：一种包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构的半导体结构。第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

88. 发明申请

US20080102566A1 MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：多层和晶体平面取向半导体基板
公开(公告)号：US20080102566A1
公开(公告)日：2008-05-01
申请号：US11969279
申请日：2008-01-04
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

89. 发明申请

US20070241412A1 BORDERLESS CONTACT STRUCTURES 有权
标题翻译：无边界接触结构
公开(公告)号：US20070241412A1
公开(公告)日：2007-10-18
申请号：US11679873
申请日：2007-02-28
申请人： Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/085
CPC分类号： H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/11 , H01L27/1104
摘要： An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PFET; a second silicide layer contacting a sidewall contact region of the second gate segment and a drain of the first PFET; a third silicide layer contacting a sidewall contact region of the first gate segment and a drain of the second NFET; a fourth silicide layer contacting a first end of the second gate segment, a drain of the first PFET and a drain of a fourth NFET; and a fifth silicide layer contacting a second end of the first gate segment and a drain of a third NFET.
摘要翻译：一个SRAM单元。该SRAM单元包括：第一PFET和第一NFET公共的第一栅极段，与第二PFET和第二NFET共用的第二栅极段; 接触第一栅极段的第一端和第二PFET的漏极的第一硅化物层; 接触第二栅极段的侧壁接触区域和第一PFET的漏极的第二硅化物层; 接触第一栅极段的侧壁接触区域和第二NFET的漏极的第三硅化物层; 接触第二栅极段的第一端的第四硅化物层，第一PFET的漏极和第四NFET的漏极; 以及接触第一栅极段的第二端和第三NFET的漏极的第五硅化物层。

90. 发明申请

US20070059891A1 Mandrel/trim alignment in SIT processing 有权
标题翻译： SIT处理中的心轴/微调对齐
公开(公告)号：US20070059891A1
公开(公告)日：2007-03-15
申请号：US11226726
申请日：2005-09-14
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Qiqing Ouyang
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Qiqing Ouyang
IPC分类号： H01L21/467
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：本文公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，其需要将修剪掩模对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式