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81. 发明授权

US08437426B2 Receiving apparatus, receiving method, and program 有权
标题翻译：接收装置，接收方法和程序
公开(公告)号：US08437426B2
公开(公告)日：2013-05-07
申请号：US12567856
申请日：2009-09-28
申请人： Hidetoshi Kawauchi , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
发明人： Hidetoshi Kawauchi , Masayuki Hattori , Toshiyuki Miyauchi , Takashi Yokokawa , Kazuhiro Shimizu , Kazuhisa Funamoto
IPC分类号： H04B1/38 , H04N7/12 , H04L27/00
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.
摘要翻译：本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。

82. 发明授权

US08363755B2 Signal receiving apparatus, method, program and system 有权
标题翻译：信号接收装置，方法，程序和系统
公开(公告)号：US08363755B2
公开(公告)日：2013-01-29
申请号：US12788398
申请日：2010-05-27
申请人： Suguru Houchi , Naoki Yoshimochi , Takuya Okamoto , Yuken Goto , Takashi Yokokawa
发明人： Suguru Houchi , Naoki Yoshimochi , Takuya Okamoto , Yuken Goto , Takashi Yokokawa
IPC分类号： H04L27/00
CPC分类号： H04L27/2662 , H04L5/0023 , H04L5/0048 , H04L25/0204 , H04L25/0226 , H04L25/0232 , H04L25/03159 , H04L27/2649 , H04L27/2675 , H04L2025/03414 , H04L2025/03426
摘要： A signal receiving apparatus includes: an acquisition section configured to acquire an Orthogonal Frequency Division Multiplexing signal resulting from combination of a plurality of signals transmitted by a plurality of signal transmitting apparatus by adoption of an Orthogonal Frequency Division Multiplexing method; and a demodulation section configured to carry out partial processing of processing to demodulate the Orthogonal Frequency Division Multiplexing signal acquired by the acquisition section by making use of either first pilot signals or second pilot signals where the first pilot signals are pilot signals extracted from the Orthogonal Frequency Division Multiplexing signal acquired by the acquisition section as signals having the same phase for all the signal transmitting apparatus, and the second pilot signals are pilot signals extracted from the Orthogonal Frequency Division Multiplexing signal acquired by the acquisition section as signals having different phases depending on the signal transmitting apparatus.
摘要翻译：信号接收装置包括：获取部，被配置为通过采用正交频分复用方法获取由多个信号发送装置发送的多个信号的组合而得到的正交频分复用信号; 以及解调部，被配置为执行处理的部分处理，以通过利用第一导频信号或第二导频信号来解调由获取部获取的正交频分复用信号，其中第一导频信号是从正交频率提取的导频信号由采集部分获取的分复用信号作为对于所有信号发送装置具有相同相位的信号，并且第二导频信号是从由采集部分获取的正交频分复用信号中提取的导频信号，作为具有不同相位的信号，取决于信号发送装置。

83. 发明申请

US20120320994A1 ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY 有权
标题翻译：编码和编码方法提供增值冗余
公开(公告)号：US20120320994A1
公开(公告)日：2012-12-20
申请号：US13579735
申请日：2011-02-18
申请人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
发明人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
IPC分类号： H04N7/56
CPC分类号： H03M13/11 , H03M13/1165 , H03M13/3761 , H03M13/6519 , H04L1/0036 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0068 , H04L1/0083 , H04L2001/0098
摘要： The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ, wherein said parity symbol addresses γ are determined according to a second address generation rule Nldpc−Kldpc+{x+m mod Ga×QIR} mod MIR if x>Nldpc−Kldpc, wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and QIR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
摘要翻译：本发明涉及一种用于将输入数据字（D）编码成码字（Z1，Z2）的纠错码的编码器，包括：编码器输入端（1451），用于接收输入数据字（D），每个输入数据字包括第一数字信号Kldpc 符号，用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4）的编码装置（1452），使得码字包括基本码字部分（B），其包括数据部分（D）和基本奇偶校验符号的第二编号Nldpc-Kldpc的基本奇偶校验部分（Pb）和包括辅助奇偶校验符号的第三数量MIR的辅助奇偶校验部分（Pa）的辅助码字部分（A），其中所述编码装置）适于i）用于根据第一代码从输入数据字（D）产生所述基本码字部分（B），其中通过在根据第一代码确定的奇偶校验符号地址处累积信息符号来生成基本奇偶校验符号地址生成规则，和ii）生成s 根据第二代码从输入数据字（D）辅助辅助码字部分（A），其中通过在奇偶校验符号地址γ处累积信息符号m来生成辅助奇偶校验符号，其中所述奇偶校验符号地址γ根据如果x> Nldpc-Kldpc，则到第二地址生成规则Nldpc-Kldpc + {x + m mod Ga×QIR} mod MIR，其中x表示对应于大小为Ga的组的第一信息符号的奇偶校验符号累加器的地址， QIR是辅助代码速率相关的预定义常数，以及用于输出所述码字（Z1，Z2）的编码器输出（1454）。

84. 发明授权

US08281205B2 LDPC decoding apparatus, decoding method and program 有权
标题翻译： LDPC解码装置，解码方法和程序
公开(公告)号：US08281205B2
公开(公告)日：2012-10-02
申请号：US12252470
申请日：2008-10-16
申请人： Takashi Yokokawa
发明人： Takashi Yokokawa
IPC分类号： H03M13/00
CPC分类号： H03M13/1168 , H03M13/1111 , H03M13/1137 , H03M13/116 , H03M13/1165 , H03M13/616 , H03M13/6508 , H03M13/6577
摘要： Disclosed herein is a decoding apparatus for decoding an LDPC code, the decoding apparatus including: a message computation section configured to carry out a process of decoding received values, where notation F denotes a non-unity measure of the integer P, and outputting F messages; a shift section configured to carry out F×F cyclic shift operations on the F messages and output F messages; a storage section configured to store the F messages and allow the stored F messages to be read out or to store F received values cited above and allow the stored F received values to be read out; and a control section configured to control an operation to supply a unit composed of the F received values to the message computation section by carrying out at least a column rearrangement process or a process equivalent to the column rearrangement process on the received values.
摘要翻译：这里公开了一种解码LDPC码的解码装置，该解码装置包括：消息计算部，被配置为执行对接收值进行解码的处理，其中，F表示整数P的非一致性度量，并输出F个消息 ; 移位部，被配置为对所述F个消息进行F×F循环移位操作，并输出F个消息; 存储部，其被配置为存储所述F个消息，并且允许所存储的F个消息被读出或存储上述引用的F个接收值，并且允许读取所存储的F个接收值; 以及控制部，被配置为通过对接收到的值执行至少一个列重排处理或与该列重排处理相当的处理来控制将由F个接收值组成的单元提供给消息计算部的操作。

85. 发明授权

US08179955B2 Low density parity check (LDPC) coding for a 32K mode interleaver in a digital video broadcasting (DVB) standard 有权
标题翻译：用于数字视频广播（DVB）标准中的32K模式交织器的低密度奇偶校验（LDPC）编码
公开(公告)号：US08179955B2
公开(公告)日：2012-05-15
申请号：US12260327
申请日：2008-10-29
申请人： Matthew Paul Athol Taylor , Samuel Asanbeng Atungsiri , Takashi Yokokawa , Makiko Yamamoto
发明人： Matthew Paul Athol Taylor , Samuel Asanbeng Atungsiri , Takashi Yokokawa , Makiko Yamamoto
IPC分类号： H03H7/30
CPC分类号： H03M13/1168 , H03M13/1137 , H03M13/1148 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/15 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H04L1/0057 , H04L1/0071 , H04L5/0007 , H04L5/0044 , H04L5/0064 , H04L27/2626 , H04L27/2647 , H04L27/34
摘要： A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.
摘要翻译：数据处理装置在正交频分复用（OFDM）符号的预定数量的副载波信号上传送数据位。数据处理装置包括奇偶校验交织器，其可操作以对通过执行LDPC编码而获得的低密度奇偶校验（LDPC）编码数据比特进行奇偶校验交织，所述LDPC编码数据比特根据LDPC码的奇偶校验矩阵，该LDPC码包括与LDPC码奇偶校验位对应的奇偶校验矩阵代码，奇偶校验矩阵具有逐步结构，使得LDPC编码数据位的奇偶校验位被交织到不同的奇偶校验位位置。映射单元将奇偶交织的比特映射到对应于OFDM子载波信号的调制方案的调制符号的数据符号上。

86. 发明授权

US08176402B2 Decoding apparatus, decoding method, and decoding program 有权
标题翻译：解码装置，解码方法和解码程序
公开(公告)号：US08176402B2
公开(公告)日：2012-05-08
申请号：US12110064
申请日：2008-04-25
申请人： Takashi Yokokawa , Yuichi Hirayama , Osamu Shinya , Satoshi Okada , Kazuhiro Oguchi
发明人： Takashi Yokokawa , Yuichi Hirayama , Osamu Shinya , Satoshi Okada , Kazuhiro Oguchi
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G11B20/1833 , G11B20/1866
摘要： A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
摘要翻译：解码装置包括存储器和接收单元，并且适于以包括奇偶校验部分的码字为单位对数据进行解码。存储器具有能够存储长度等于一个码字的长度的至少数据的存储容量。接收单元以比特交织形式接收码字的元素作为接收值，对接收到的值执行比特解交织和奇偶校验，并将所得到的接收值存储在存储器中。

87. 发明授权

US08045945B2 Reception apparatus, reception method and program 有权
标题翻译：接收设备，接收方法和程序
公开(公告)号：US08045945B2
公开(公告)日：2011-10-25
申请号：US12393093
申请日：2009-02-26
申请人： Hidetoshi Kawauchi , Tadaaki Yuba , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Tamotsu Ikeda , Koji Naniwada , Kazuhiro Shimizu , Lachlan Bruce Michael
发明人： Hidetoshi Kawauchi , Tadaaki Yuba , Toshiyuki Miyauchi , Takashi Yokokawa , Takuya Okamoto , Tamotsu Ikeda , Koji Naniwada , Kazuhiro Shimizu , Lachlan Bruce Michael
IPC分类号： H04B1/10
CPC分类号： H04B1/1036 , H04L5/0048 , H04L25/0216 , H04L25/0232
摘要： A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.
摘要翻译：一种接收装置，包括提取部分; 传输线特性估计部; 插值部分; 赔偿部分; 检测部; 和选择部分。

88. 发明授权

US07986615B2 Demodulating circuit, demodulating method, program, and receiving device 有权
标题翻译：解调电路，解调方法，程序和接收装置
公开(公告)号：US07986615B2
公开(公告)日：2011-07-26
申请号：US12403436
申请日：2009-03-13
申请人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takashi Horiguti , Naoki Yoshimochi , Yasuhiro Iida , Satoru Hori
发明人： Hidetoshi Kawauchi , Toshiyuki Miyauchi , Takashi Yokokawa , Takashi Horiguti , Naoki Yoshimochi , Yasuhiro Iida , Satoru Hori
IPC分类号： H04J11/00
CPC分类号： H04L27/2647 , H04L25/0232 , H04L25/03821
摘要： A demodulating circuit including: an FFT processing section; an intercarrier interferential component removing section; an extracting section; a transmission path characteristics estimating section; an interpolating section; a symbol sequence estimating section; and an interference replica generating section.
摘要翻译：一种解调电路，包括：FFT处理部分; 一个载波间干扰部分去除部分; 提取部分; 传输路径特性估计部分; 内插部分一个符号序列估计部分; 和干扰复制产生部分。

89. 发明申请

US20100281329A1 DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM 有权
标题翻译：数据处理设备，数据处理方法和程序
公开(公告)号：US20100281329A1
公开(公告)日：2010-11-04
申请号：US12743487
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/2703 , H03M13/2707 , H03M13/271 , H03M13/6552 , H03M13/6555 , H04L1/0057
摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.
摘要翻译：本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织存储器的每列的存储器方向。本发明可以应用于例如用于发送LDPC码的发送装置。

90. 发明授权

US07657820B2 Decoding device and decoding method 失效
标题翻译：解码设备和解码方法
公开(公告)号：US07657820B2
公开(公告)日：2010-02-02
申请号：US11409237
申请日：2006-04-24
申请人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
发明人： Takashi Yokokawa , Yuji Shinohara , Osamu Shinya
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/118 , H03M13/6577
摘要： A decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device may include a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse function of the nonlinear function; and a second operation unit for performing a variable node operation for decoding the LDPC code. The first operation unit includes a first converting unit for converting a first quantization value assigned to a numerical value into a second quantization value representing a numerical value with a higher precision than the first quantization value, and a second converting unit for converting the second quantization value into the first quantization value.
摘要翻译：一种用于解码LDPC（低密度奇偶校验）码的解码装置。解码装置可以包括用于执行用于对LDPC码进行解码的校验节点操作的第一操作单元，该操作包括非线性函数的操作和非线性函数的反函数的操作; 以及第二操作单元，用于执行用于对LDPC码进行解码的可变节点操作。第一操作单元包括：第一转换单元，用于将分配给数值的第一量化值转换成表示具有比第一量化值更高的精度的数值的第二量化值;以及第二转换单元，用于将第二量化值进入第一个量化值。

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