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1. 发明授权

US08176402B2 Decoding apparatus, decoding method, and decoding program 有权
标题翻译：解码装置，解码方法和解码程序
公开(公告)号：US08176402B2
公开(公告)日：2012-05-08
申请号：US12110064
申请日：2008-04-25
申请人： Takashi Yokokawa , Yuichi Hirayama , Osamu Shinya , Satoshi Okada , Kazuhiro Oguchi
发明人： Takashi Yokokawa , Yuichi Hirayama , Osamu Shinya , Satoshi Okada , Kazuhiro Oguchi
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G11B20/1833 , G11B20/1866
摘要： A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
摘要翻译：解码装置包括存储器和接收单元，并且适于以包括奇偶校验部分的码字为单位对数据进行解码。存储器具有能够存储长度等于一个码字的长度的至少数据的存储容量。接收单元以比特交织形式接收码字的元素作为接收值，对接收到的值执行比特解交织和奇偶校验，并将所得到的接收值存储在存储器中。

2. 发明申请

US20080270876A1 Decoding Apparatus, Decoding Method, and Decoding Program 有权
标题翻译：解码装置，解码方法和解码程序
公开(公告)号：US20080270876A1
公开(公告)日：2008-10-30
申请号：US12110064
申请日：2008-04-25
申请人： Takashi Yokokawa , Yuichi Hirayama , Osamu Shinya , Satoshi Okada , Kazuhiro Oguchi
发明人： Takashi Yokokawa , Yuichi Hirayama , Osamu Shinya , Satoshi Okada , Kazuhiro Oguchi
IPC分类号： H03M13/27 , G06F11/10
CPC分类号： G06F11/1008 , G11B20/1833 , G11B20/1866
摘要： A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
摘要翻译：解码装置包括存储器和接收单元，并且适于以包括奇偶校验部分的码字为单位对数据进行解码。存储器具有能够存储长度等于一个码字的长度的至少数据的存储容量。接收单元以比特交织形式接收码字的元素作为接收值，对接收到的值执行比特解交织和奇偶校验，并将所得到的接收值存储在存储器中。

3. 发明授权

US08209581B2 Receiving apparatus and method and program for receiving and decoding a low density parity check code 有权
标题翻译：用于接收和解码低密度奇偶校验码的接收装置和方法和程序
公开(公告)号：US08209581B2
公开(公告)日：2012-06-26
申请号：US12253347
申请日：2008-10-17
申请人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
发明人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
IPC分类号： G06F11/00
CPC分类号： H03M13/11 , H04L1/0052 , H04L1/0057 , H04L1/007
摘要： A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.
摘要翻译：一种接收装置，包括：LDPC解码器，被配置为解码所述数据信号和所述传输控制信号;数据信号输入缓冲器，布置在所述LDPC解码器之前并被配置为保持所述接收的数据信号;以及传输控制信号输入缓冲器， LDPC解码器，被配置为保持所接收的发送控制信号，以及控制器，被配置为选择保持在数据信号输入缓冲器中的数据信号中的一个和保持在发送控制信号输入缓冲器中的发送控制信号作为经解码的信号;以及将所选择的信号发送到LDPC解码器，以使LDPC解码器对经过解码的信号进行解码。

4. 发明申请

US20090106622A1 RECEIVING APPARATUS AND METHOD AND PROGRAM 有权
标题翻译：接收装置和方法与程序
公开(公告)号：US20090106622A1
公开(公告)日：2009-04-23
申请号：US12253347
申请日：2008-10-17
申请人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
发明人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/11 , H04L1/0052 , H04L1/0057 , H04L1/007
摘要： A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.
摘要翻译：一种接收装置，包括：LDPC解码器，被配置为解码所述数据信号和所述传输控制信号;数据信号输入缓冲器，布置在所述LDPC解码器之前并被配置为保持所述接收的数据信号;以及传输控制信号输入缓冲器， LDPC解码器，被配置为保持所接收的发送控制信号，以及控制器，被配置为选择保持在数据信号输入缓冲器中的数据信号中的一个和保持在发送控制信号输入缓冲器中的发送控制信号作为经解码的信号;以及将所选择的信号发送到LDPC解码器，以使LDPC解码器对经过解码的信号进行解码。

5. 发明申请

US20120110415A1 DECODING APPARATUS, METHOD, AND PROGRAM 审中-公开
标题翻译：解码设备，方法和程序
公开(公告)号：US20120110415A1
公开(公告)日：2012-05-03
申请号：US13238397
申请日：2011-09-21
申请人： Takashi Yokokawa , Osamu Shinya , Yutaka Nakada , Ryoji Ikegaya
发明人： Takashi Yokokawa , Osamu Shinya , Yutaka Nakada , Ryoji Ikegaya
IPC分类号： G11C29/42 , G06F11/10
CPC分类号： H03M13/152 , H03M13/65 , H03M13/6502
摘要： The present disclosure provides a decoding apparatus including, a storage section configured to store a reception value, a detection section configured to detect an error in the reception value, an error correction section configured to correct an error detected by the detection section with respect to the reception value, and a control section configured to control reading of the reception value from the storage section, wherein the control section controls first reading such that the reception value is read into the detection section and, after detection of an error by the detection section, second reading such that substantially the same reception value as that in the first reading is read into the error correction section.
摘要翻译：本公开提供了一种解码装置，包括：存储部，被配置为存储接收值;检测部，被配置为检测接收值中的误差;纠错部，被配置为校正由所述检测部检测到的相对于接收值，以及控制部，其被配置为控制从所述存储部读取接收值，其中，所述控制部控制第一读取，使得所述接收值被读入所述检测部，并且在检测部检测到错误之后，第二读取使得与第一读取中基本上相同的接收值被读入错误校正部分。

6. 发明申请

US20090217121A1 Decoding Apparatus and Decoding Method 有权
标题翻译：解码装置和解码方法
公开(公告)号：US20090217121A1
公开(公告)日：2009-08-27
申请号：US11912481
申请日：2006-04-20
申请人： Takashi Yokokawa , Toshiyuki Miyauchi , Osamu Shinya
发明人： Takashi Yokokawa , Toshiyuki Miyauchi , Osamu Shinya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
摘要翻译：解码装置和解码方法技术领域本发明涉及一种能够在防止解码装置的电路规模增大的同时高精度地解码LDPC码的解码装置和解码方法。计算部分1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101来执行与三个校验节点处理相对应的第一计算处理，并且存储第一在解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收（数字）卫星广播的调谐器。

7. 发明授权

US09172497B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09172497B2
公开(公告)日：2015-10-27
申请号：US13885557
申请日：2011-11-14
申请人： Osamu Shinya , Takashi Yokokawa , Lachlan Bruce Michael
发明人： Osamu Shinya , Takashi Yokokawa , Lachlan Bruce Michael
IPC分类号： H04L1/00 , H03M13/11 , H03M13/15 , H03M13/25 , H03M13/00
CPC分类号： H04L1/004 , H03M13/1102 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/618 , H03M13/6362 , H03M13/6552 , H04L1/0043 , H04L1/0052 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L1/0072
摘要： A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.
摘要翻译：能够容易地处理其PAPR的控制数据的数据处理装置和数据处理方法。在传输装置中，焊盘将用于以零作为解调的解调所需的数据作为伪数据，并且扰频器对填充的控制数据进行加扰（后置填充控制数据）。替换单元用伪数据替换加密的后置填充控制数据中的加密伪数据，并且BCH编码器和LDPC编码器对通过替换获得的替换数据执行BCH编码和LDPC编码作为纠错编码。缩短单元通过删除包含在LDPC码中的伪数据并对该LDPC码的奇偶校验位进行穿孔来进行缩短。例如，在控制数据经受纠错编码的情况下可以应用该装置。

8. 发明授权

US08375268B2 Receiving apparatus, receiving method, computer program, and receiving system 失效
标题翻译：接收装置，接收方法，计算机程序和接收系统
公开(公告)号：US08375268B2
公开(公告)日：2013-02-12
申请号：US12888071
申请日：2010-09-22
申请人： Osamu Shinya , Takashi Yokokawa , Naoki Yoshimochi
发明人： Osamu Shinya , Takashi Yokokawa , Naoki Yoshimochi
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H03M13/1102 , H03M13/152 , H03M13/2906 , H03M13/6552 , H04L1/0057
摘要： A receiving apparatus includes: a first decoding means for performing, every time frame data in which an inner code and an outer code are used as error correction codes is transmitted thereto, decoding processing employing the inner code and outputting decoded data; a storing means for storing the decoded data; a second decoding means for applying decoding processing employing the outer code to the decoded data; and a control means for controlling storage and output of the decoded data in and from the storing means to suspend, while the control means causes the storing means to output first decoded data as the decoded data of a decoding result of first frame data to the second decoding means, when the first decoding means starts output of second decoded data as the decoded data of a decoding result of second frame data following the first frame data, the output of the first decoded data to the second decoding means and cause the storing means to store the second decoded data and, when the storage of the second decoded data ends, cause the storing means to resume the output of the first decoded data to the second decoding means.
摘要翻译：一种接收装置，包括：第一解码装置，用于在其中发送使用内部码和外部码作为纠错码的每个时间帧数据，使用内部码来解码处理并输出解码数据; 存储装置，用于存储解码数据; 第二解码装置，用于将采用外部码的解码处理应用于解码数据; 以及控制装置，用于在所述存储装置使所述存储装置将所述第一解码数据的解码数据作为所述第一帧数据的解码结果的解码数据输出到所述第二帧数据的同时，解码装置，当第一解码装置开始输出第二解码数据作为第一帧数据之后的第二帧数据的解码结果的解码数据时，将第一解码数据输出到第二解码装置，并使存储装置存储第二解码数据，并且当第二解码数据的存储结束时，使存储装置恢复第一解码数据的输出到第二解码装置。

9. 发明授权

US08166363B2 Decoding device and method 失效
标题翻译：解码设备和方法
公开(公告)号：US08166363B2
公开(公告)日：2012-04-24
申请号：US12066641
申请日：2006-09-07
申请人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
发明人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
IPC分类号： H03M13/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译：一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。校验节点计算器（181）执行包括非线性函数的计算的校验节点计算（x）及其非线性函数的反函数＆phgr（-1），以解码LDPC码。可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。校验节点计算器（181）具有LUT，其接收表示具有固定量化宽度的数值的定点量化值，并将非线性函数＆amp;（x）的计算结果作为半浮点数量化值，其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数的计算结果＆phgr; -1（ x）作为固定点量化值。本发明可以应用于例如用于接收卫星广播的调谐器。

10. 发明申请

US20090304111A1 Decoding Device and Method 失效
标题翻译：解码设备和方法
公开(公告)号：US20090304111A1
公开(公告)日：2009-12-10
申请号：US12066641
申请日：2006-09-07
申请人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
发明人： Osamu Shinya , Takashi Yokokawa , Yuji Shinohara , Toshiyuki Miyauchi
IPC分类号： H03K9/00
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/118 , H03M13/6577 , H04L1/0057
摘要： A decoding device and method for decoding an LDPC code with high accuracy while suppressing an increase of the scale of a device. A check node calculator (181) performs check node calculations including calculations of a nonlinear function φ(x) and its inverse function φ−1(x) of the nonlinear function so as to decode an LDPC code. A variable node calculator (103) performs variable node calculation of a variable node so as to decode the LDPC code. The check node calculator (181) has an LUT which receives a fixed-point quantized value expressing a numerical value with a fixed quantization width and outputs the result of the calculation of the nonlinear function φ(x) as a semi-floating point quantized value which is a bit sequence expressing a numerical value with a quantization width determined by a part of a bit sequence and an LUT which receives a semi-floating point quantized value and outputs the result of the calculation of the inverse function φ−1(x) as a fixed point quantized value. The invention can be applied to e.g., a tuner for receiving a satellite broadcast.
摘要翻译：一种用于在抑制设备规模增加的同时高精度地解码LDPC码的解码装置和方法。校验节点计算器（181）执行包括非线性函数phi（x）及其反函数phi-1（x）的计算的校验节点计算，以解码LDPC码。可变节点计算器（103）执行变量节点的可变节点计算，以解码LDPC码。校验节点计算器（181）具有LUT，其接收具有固定量化宽度的表示数值的定点量化值，并将非线性函数phi（x）的计算结果输出为半浮点量化值其是表示具有由位序列的一部分确定的量化宽度的数值的位序列和接收半浮点量化值的LUT，并输出反函数phi-1（x）的计算结果，作为固定点量化值。本发明可以应用于例如用于接收卫星广播的调谐器。

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