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81. 发明授权

US06906973B1 Bit-line droop reduction 失效
标题翻译：位线下垂减少
公开(公告)号：US06906973B1
公开(公告)日：2005-06-14
申请号：US10746148
申请日：2003-12-24
申请人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien L. Lu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C7/00 , G11C7/12
CPC分类号： G11C7/12
摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.
摘要翻译：一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电，使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

82. 发明授权

US06831871B2 Stable memory cell read 失效
公开(公告)号：US06831871B2
公开(公告)日：2004-12-14
申请号：US10334456
申请日：2002-12-30
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C2207/2281
摘要： According to some embodiments, provided are a memory cell, a bit-line coupled to the memory cell, a pre-charge circuit coupled to the bit-line to pre-charge the bit-line, and a discharge device coupled to the bit-line to discharge the bit-line prior to a read of the memory cell.

83. 发明授权

US06806739B2 Time-borrowing N-only clocked cycle latch 有权
公开(公告)号：US06806739B2
公开(公告)日：2004-10-19
申请号：US10330544
申请日：2002-12-30
申请人： Dejan Markovic , James W. Tschanz , Vivek K. De
发明人： Dejan Markovic , James W. Tschanz , Vivek K. De
IPC分类号： H03K19094
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/037 , H03K3/356156
摘要： A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

84. 发明授权

US06683467B1 Method and apparatus for providing rotational burn-in stress testing 失效
标题翻译：提供旋转老化压力测试的方法和装置
公开(公告)号：US06683467B1
公开(公告)日：2004-01-27
申请号：US09672689
申请日：2000-09-29
申请人： Ali Keshavarzi , David M. Wu , Yibin Ye , Vivek K. De
发明人： Ali Keshavarzi , David M. Wu , Yibin Ye , Vivek K. De
IPC分类号： G01R3102
CPC分类号： G01R31/2817
摘要： A method and device are provided for stress testing a chip. The chip may be partitioned into at least a first block and a second block. Burn-in stress testing may be performed on electronic devices within the first block without simultaneously performing burn-in stress testing on electronic devices within the second block. A burn-in stress testing device may perform the burn-in testing. A control device may be coupled to the burn-in stress testing device to enable burn-in stress testing on electronic devices within at least the first block of the chip without simultaneously enabling burn-in stress testing on the second block of the chip.
摘要翻译：提供了一种用于芯片压力测试的方法和装置。芯片可以被划分成至少第一块和第二块。老化压力测试可以在第一块内的电子设备上执行，而不对第二块内的电子设备进行同时进行老化压力测试。老化压力测试装置可执行老化测试。控制装置可以耦合到老化压力测试装置，以在芯片的至少第一块内的电子装置上实现耐久性测试，而不必在芯片的第二块上同时进行老化压力测试。

85. 发明授权

US06552887B1 Voltage dependent capacitor configuration for higher soft error rate tolerance 有权
标题翻译：电压相关电容器配置，用于更高的软错误率容差
公开(公告)号：US06552887B1
公开(公告)日：2003-04-22
申请号：US09608457
申请日：2000-06-29
申请人： Tanay Karnik , Rajendran Nair , Vivek K. De
发明人： Tanay Karnik , Rajendran Nair , Vivek K. De
IPC分类号： G11C1140
CPC分类号： G11C5/005 , G11C11/401 , H01L27/0808
摘要： A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.
摘要翻译：公开了一种用于在集成电路中提供软错误率容限的电压相关电容器。在一个实施例中，使用并联n-p电压依赖电容器来保护节点免受噪声。在另一个实施例中，使用nFET-nWell电压相关电容器来提供具有减小的面积的软误差容限电容器。

86. 发明授权

US06518796B1 Dynamic CMOS circuits with individually adjustable noise immunity 失效
标题翻译：动态CMOS电路具有独立可调的抗噪声能力
公开(公告)号：US06518796B1
公开(公告)日：2003-02-11
申请号：US09607495
申请日：2000-06-30
申请人： Mircea R. Stan , Vivek K. De
发明人： Mircea R. Stan , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A system of individually adjusting noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network comprises identifying precharge nodes of the dynamic circuit requiring a reduction of noise. Then further identifying NMOS transistor drains connected to the respective precharge nodes, then creating a pull-up network of PMOS transistors for the precharge nodes, respectively. After creating a pull-up network of PMOS transistors, the system further includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve the noise immunity and performance of the dynamic circuit. After completing the arranging of the order of the PMOS transistors, the system can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes, respectively.
摘要翻译：包括并行或串联并联下拉网络的动态电路的每个输入的单独调节噪声抗扰度的系统包括识别要求降低噪声的动态电路的预充电节点。然后进一步识别连接到各个预充电节点的NMOS晶体管漏极，然后分别为预充电节点创建PMOS晶体管的上拉网络。在创建PMOS晶体管的上拉网络之后，该系统还包括布置与各个预充电节点相对应的PMOS晶体管的阶数，以提高动态电路的抗噪声性能和性能。在完成了PMOS晶体管的顺序排列之后，系统还可以包括分别对PMOS晶体管进行尺寸调整以实现预充电节点所需的噪声减小。

87. 发明授权

US06169419A Method and apparatus for reducing standby leakage current using a transistor stack effect 有权
标题翻译：使用晶体管堆叠效应来减少备用漏电流的方法和装置
公开(公告)号：US06169419A
公开(公告)日：2001-01-02
申请号：US09151177
申请日：1998-09-10
申请人： Vivek K. De , Yibin Ye
发明人： Vivek K. De , Yibin Ye
IPC分类号： H03K190948
CPC分类号： H03K19/0016
摘要： Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.
摘要翻译：使用晶体管堆叠效应减少内部电路块中的备用漏电流。对于一个实施例，一种装置包括要耦合到包括多个逻辑门的电路块的备用泄漏减小电路。备用泄漏降低电路在电路块的待机模式期间在多个逻辑门中的每一个处引起堆叠效应，通过关闭两个或更多个相同类型（n型或p型）的串联耦合晶体管每个逻辑门。

88. 发明授权

US09484917B2 Digital clamp for state retention 有权
标题翻译：数字钳位状态保持
公开(公告)号：US09484917B2
公开(公告)日：2016-11-01
申请号：US13718372
申请日：2012-12-18
申请人： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
发明人： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
IPC分类号： G05F1/10 , G05F1/59 , H03K19/00 , G05F1/46
CPC分类号： H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
摘要： Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
摘要翻译：描述了一种装置，其包括：耦合在第一电源和第二电源之间的夹具; 以及用于与第二电源操作的电路，其中当所述设备进入低功率模式时，所述钳位器可操作以调节所述第二电源。

89. 发明授权

US09063730B2 Performing variation-aware profiling and dynamic core allocation for a many-core processor 有权
标题翻译：为多核处理器执行变化感知分析和动态核心分配
公开(公告)号：US09063730B2
公开(公告)日：2015-06-23
申请号：US12972985
申请日：2010-12-20
申请人： Saurabh Dighe , Sriram R. Vangal , Nitin Y. Borkar , Vivek K. De
发明人： Saurabh Dighe , Sriram R. Vangal , Nitin Y. Borkar , Vivek K. De
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F1/3206 , G06F1/329 , G06F9/4893 , Y02D10/24
摘要： In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核心的处理器，每个核心具有自检电路，以确定相应核心的频率分布和泄漏功率分布。反过来，调度器被耦合以接收频率分布和泄漏功率分布，并且基于频率分布和泄漏功率分布来在至少一些核上调度应用。描述和要求保护其他实施例。

90. 发明申请

US20090089562A1 Methods and apparatuses for reducing power consumption of processor switch operations 有权
标题翻译：降低处理器开关操作功耗的方法和装置
公开(公告)号：US20090089562A1
公开(公告)日：2009-04-02
申请号：US11904395
申请日：2007-09-27
申请人： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
发明人： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
IPC分类号： G06F9/312
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
摘要翻译：公开了用于降低处理器开关操作功耗的方法和装置。一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。

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