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81. 发明授权

US06735681B2 Processor and branch prediction method 失效
标题翻译：处理器和分支预测方法
公开(公告)号：US06735681B2
公开(公告)日：2004-05-11
申请号：US09794063
申请日：2001-02-28
申请人： Shigehiro Asano , Takashi Yoshikawa
发明人： Shigehiro Asano , Takashi Yoshikawa
IPC分类号： G06F1200
CPC分类号： G06F9/382 , G06F9/3846 , G06F9/3848
摘要： A next address computing section contains a selector and is connected to an instruction cache. The instruction cache maintains a predecode result of a branch instruction or predefined settings for a field in this branch instruction. Based on this information maintained in the instruction cache, the selector determines whether the compiler performed a branch prediction about the branch instruction or could not perform that branch prediction. When the compiler could not perform the branch prediction, the selector selects an output from a conditional branch prediction device (saturation counter section). When the compiler performed the branch prediction, the selector selects a prediction result by the compiler for a prediction in Agree mode. These selection results are used for setting a value of a register holding the next address. Based on this next-address register value, an instruction is fetched from the cache then inserted into a pipeline.
摘要翻译：下一个地址计算部分包含选择器并连接到指令高速缓存。指令高速缓存维护分支指令的预解码结果或此分支指令中字段的预定义设置。基于保存在指令高速缓存中的信息，选择器确定编译器是否执行关于分支指令的分支预测或者不能执行该分支预测。当编译器不能执行分支预测时，选择器从条件分支预测装置（饱和度计数器部分）中选择输出。当编译器执行分支预测时，选择器在同意模式下选择编译器预测的预测结果。这些选择结果用于设置保存下一个地址的寄存器的值。基于该下一个地址寄存器值，从缓存中取出指令，然后插入到管道中。

82. 发明授权

US06327614B1 Network server device and file management system using cache associated with network interface processors for redirecting requested information between connection networks 失效
标题翻译：使用与网络接口处理器相关联的缓存的网络服务器设备和文件管理系统在连接网络之间重定向所请求的信息
公开(公告)号：US06327614B1
公开(公告)日：2001-12-04
申请号：US09154031
申请日：1998-09-16
申请人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
发明人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
IPC分类号： G06F15167
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/067 , H04L67/02 , H04L67/28 , H04L67/2814 , H04L67/2842 , H04L67/2895
摘要： A server device is formed by a plurality of network interface processors connected to a network, each network interface processor having a network interface local memory functioning as a cache memory for storing a part of server data and a network interface local processor, at least one storage interface processor connected with a storage device for storing the server data, and a connection network for connecting the network interface processors and the storage interface processor. In this server device, the network interface local processor of one network interface processor carries out a control processing such that a requested data stored In the network interface local memory of the one network Interface processor is transmitted to the network when a request received from the network at the one network interface processor satisfies a prescribed first condition, and the request is given to the storage interface processor via the connection network when the request satisfies a prescribed second condition and the requested data is transmitted to the network upon receiving the requested data returned from the storage interface processor to the one network interface processor via the connection network in response to the request.
摘要翻译：服务器设备由连接到网络的多个网络接口处理器形成，每个网络接口处理器具有用作存储服务器数据的一部分的高速缓存存储器的网络接口本地存储器和网络接口本地处理器，至少一个存储器与用于存储服务器数据的存储设备连接的接口处理器，以及用于连接网络接口处理器和存储接口处理器的连接网络。在该服务器装置中，一个网络接口处理器的网络接口本地处理器执行控制处理，使得当从网络接收到请求时，将存储在一个网络接口处理器的网络接口本地存储器中的所请求数据发送到网络在一个网络接口处理器满足规定的第一条件，并且当请求满足规定的第二条件时，经由连接网络将该请求提供给存储接口处理器，并且在接收到从所请求的数据返回时请求的数据被发送到网络所述存储接口处理器响应于所述请求经由所述连接网络连接到所述一个网络接口处理器。

83. 发明授权

US5996014A Distribution multimedia server system using shared disk arrays connected in a chain and having two ports each that are striped with digitalized video data 失效
标题翻译：分发多媒体服务器系统使用连接在链中的共享磁盘阵列，并具有两个端口，每个端口都带有数字化视频数据
公开(公告)号：US5996014A
公开(公告)日：1999-11-30
申请号：US959844
申请日：1997-10-29
申请人： Ikuo Uchihori , Shigehiro Asano , Masayuki Takakuwa , Tatsunori Kanai
发明人： Ikuo Uchihori , Shigehiro Asano , Masayuki Takakuwa , Tatsunori Kanai
IPC分类号： G06F3/06 , G06F13/00 , G06F15/16 , G11B19/02 , H04N21/218 , H04N21/2315
CPC分类号： H04N21/2182 , H04N21/222
摘要： The shared disk array which incorporates a plurality of disk apparatus storing the contents including the digitized video data and a plurality of element servers are connected to the shared channel network suitable for the multi-initiator architecture, whereby each of the element servers can physically share the shared disk array via the shared channel network. Further, each of the element servers is provided with the network interface suitable for the high-speed transmission and the band-width reservation, so that the contents stored in the shared disk array are read out in response to the request form the client, thus being output of the communication network via the network interface.
摘要翻译：包含存储包括数字化视频数据的内容的多个磁盘装置的共享磁盘阵列和多个元件服务器连接到适合于多启动器架构的共享信道网络，由此每个元件服务器可以物理共享共享磁盘阵列通过共享通道网络。此外，每个元件服务器设置有适于高速传输和带宽预留的网络接口，使得响应于客户端的请求读出存储在共享磁盘阵列中的内容，因此通过网络接口输出通信网络。

84. 发明授权

US5744535A Polypropylene resin composition for exterior parts of automobile 失效
标题翻译：汽车外部用聚丙烯树脂组合物
公开(公告)号：US5744535A
公开(公告)日：1998-04-28
申请号：US727105
申请日：1996-10-08
申请人： Tomohiko Akagawa , Ikunori Sakai , Shigehiro Asano
发明人： Tomohiko Akagawa , Ikunori Sakai , Shigehiro Asano
IPC分类号： C08L53/00 , C08K3/34
CPC分类号： C08L53/00
摘要： A polypropylene resin composition having a high moldability and capable of forming therefrom shaped articles having excellent surface hardness, thermal deformation resistance and low temperature impact resistance includes (A) 35-74 wt % of a crystalline ethylene-propylene block copolymer with an ethylene content of 0.5-15 wt %, an isotactic pentad fractional propylene of 96% or more and a MFR of 40-80 g/10 min. (230.degree. C., 2160 g); (B) 21-40 wt % of an ethylene-.alpha.-olefin copolymer produced by using a single site catalyst and having an .alpha.-olefin content of 70 mol % or more, a ratio (Mw/Mn) of 2.5 or less, and a ratio (MI.sub.10 /MI.sub.2.16) of 6 to 15; and (C) 5-25 wt % of a talc particle component having an average particle size of 3-7 .mu.m.
摘要翻译：具有高成型性并且能够形成具有优异的表面硬度，耐热变形性和耐低温冲击性的成形制品的聚丙烯树脂组合物包括（A）35-74重量％的乙烯含量的结晶乙烯 - 丙烯嵌段共聚物 0.5-15重量％，全同立构五单元组分数丙烯为96％以上，MFR为40〜80g / 10分钟。（230℃，2160g）; （B）21-40重量％的使用单中心催化剂制备的α-烯烃含量为70摩尔％以上，（Mw / Mn）为2.5以下的乙烯-α-烯烃共聚物，和比例（MI10 / MI2.16）为6至15; 和（C）5-25重量％的平均粒径为3-7μm的滑石颗粒组分。

85. 发明授权

US5627987A Memory management and protection system for virtual memory in computer system 失效
标题翻译：计算机系统虚拟内存的内存管理和保护系统
公开(公告)号：US5627987A
公开(公告)日：1997-05-06
申请号：US21098
申请日：1993-02-23
申请人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
发明人： Hiroshi Nozue , Mitsuo Saito , Kenichi Maeda , Shigehiro Asano , Toshio Okamoto , Shin Sungho , Hideo Segawa
IPC分类号： G06F12/10 , G06F12/14 , G06F12/00
CPC分类号： G06F12/1458 , G06F12/109 , G06F12/1483 , G06F12/1491 , G06F2212/656
摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.
摘要翻译：一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序，将搜索与当前节目号匹配的那个。此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

86. 发明授权

US08937844B2 Apparatus for generating write data and readout data 有权
标题翻译：用于产生写入数据和读出数据的装置
公开(公告)号：US08937844B2
公开(公告)日：2015-01-20
申请号：US13406945
申请日：2012-02-28
申请人： Shigehiro Asano , Toshikatsu Hida
发明人： Shigehiro Asano , Toshikatsu Hida
IPC分类号： G11C29/00 , G11C11/34 , G11C7/10 , G11C29/44
CPC分类号： G11C7/1036 , G11C29/848 , G11C2029/4402
摘要： An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information and the defective information. The second storage has storage regions in a number larger than the first number. The input unit inputs data to the second storage by the first number at a time. The shift number determining unit determines a shift number. The output unit outputs the data stored in the storage regions which is after a head storage region by the shift number, as the data is to be supplied to the data line having no defect sector based upon the defective information, and outputs information that differs from the data to the defective data line.
摘要翻译：根据实施例的装置包括第一存储器，第二存储器，输入单元，位移号确定单元和输出单元。第一存储器在识别信息和缺陷信息相关联的同时存储扇区的识别信息和指示数据线上存在缺陷的缺陷信息。第二存储器具有大于第一数量的存储区域。输入单元一次以第一个数字将数据输入到第二个存储器。换档号确定单元确定换档号码。输出单元根据缺陷信息将存储在头部存储区域之后的存储区域中的数据输出到基于缺陷信息的数据被提供给没有缺陷扇区的数据，并输出不同于数据到有缺陷的数据线。

87. 发明授权

US08719615B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08719615B2
公开(公告)日：2014-05-06
申请号：US13064316
申请日：2011-03-17
申请人： Yohei Hasegawa , Yutaka Yamada , Takashi Yoshikawa , Shigehiro Asano
发明人： Yohei Hasegawa , Yutaka Yamada , Takashi Yoshikawa , Shigehiro Asano
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F9/3887 , G06F9/3893
摘要： A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.
摘要翻译：半导体器件与某个时钟信号同步地进行操作。该半导体装置包括用于输出操作控制信息的控制单元，用于存储数据的存储单元，用于根据第一操作控制信息对第一数据执行操作的第一操作单元和用于对第二数据执行操作的第二操作单元根据第二操作控制信息。第一操作单元包括多个操作电路。构成整个运算电路的逻辑门的数量为m。第二操作单元包括其中逻辑门数为n（n> m）的至少一个操作电路。操作单元的总延迟或操作单元的总延迟中的每一个被设置为等于或小于时钟信号的周期的值。

88. 发明授权

US08612721B2 Semiconductor memory controlling device 有权
标题翻译：半导体存储器控制装置
公开(公告)号：US08612721B2
公开(公告)日：2013-12-17
申请号：US13037970
申请日：2011-03-01
申请人： Shigehiro Asano , Shinichi Kanno , Kenichiro Yoshii
发明人： Shigehiro Asano , Shinichi Kanno , Kenichiro Yoshii
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
摘要翻译：根据一个实施例，根据信息处理器的要求，半导体存储控制器以预定单位将多条数据写入在半导体芯片的存储区域内的擦除区域中没有数据写入的存储位置。作为其子集的第三表和第二表包括各自表示半导体芯片内的每个数据的存储位置的物理地址。第一表包括指定第二表条目的信息或指定第三表条目的信息。半导体存储控制器将第一和第二表记录到易失性存储器中，或将第一表记录到易失性存储器中，将第三表记录到非易失性存储器中。

89. 发明授权

US08611368B2 Controlling bandwidth reservations method and apparatus 失效
公开(公告)号：US08611368B2
公开(公告)日：2013-12-17
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： H04L12/43 , H04L12/28
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

90. 发明授权

US08495336B2 Controller, data storage device, and program product 有权
标题翻译：控制器，数据存储设备和程序产品
公开(公告)号：US08495336B2
公开(公告)日：2013-07-23
申请号：US12883796
申请日：2010-09-16
申请人： Kazuhiro Fukutomi , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro Fukutomi , Kenichiro Yoshii , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F13/12
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0611 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F3/0688 , G06F12/00 , G06F12/16 , G06F2212/1016 , G06F2212/214 , G06F2212/7202 , G06F2212/7205
摘要： According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
摘要翻译：根据一个实施例，写指令单元指示数据存取单元在由第一物理地址指示的数据存储单元的存储区中写入对象数据，指示管理信息访问单元更新地址转换信息，以及指示第一个访问单元更新第一个物理地址。压缩单元提取压缩对象数据的物理地址，指示数据访问单元读取由物理地址指示的数据存储单元的存储区域中存储的压缩对象数据，指示数据存取单元写入压缩对象数据在由第二物理地址指示的数据存储单元的存储区域中，指示管理信息存取单元更新地址转换信息，并指示第二存取单元更新第二物理地址。

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