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1. 发明授权

US06611870B1 Server device and communication connection scheme using network interface processors 失效
标题翻译：使用网络接口处理器的服务器设备和通信连接方案
公开(公告)号：US06611870B1
公开(公告)日：2003-08-26
申请号：US09136513
申请日：1998-08-19
申请人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
发明人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
IPC分类号： G06F1516
CPC分类号： G06F13/385
摘要： A server device and a communication connection scheme capable of expanding the memory bandwidth and thereby expanding the power to transmit Web data to the network are disclosed. Network cards are detachably attached to a host machine (main machine). Each network card contains a processor, a memory, and a network interface unit, where data are transmitted to the network from a memory on the network card and the memory bandwidth expansion is realized by the presence of a plurality of network cards. In addition, using a memory of the network card as a cache, the load on the host machine is reduced by transmitting data from this memory to the network when the data exists on the memory and a certain condition is satisfied.
摘要翻译：公开了能够扩展存储器带宽并由此扩展将网络数据传输到网络的功能的服务器设备和通信连接方案。网卡可拆卸地连接到主机（主机）。每个网卡包含处理器，存储器和网络接口单元，其中数据从网卡上的存储器发送到网络，并且通过存在多个网卡来实现存储器带宽扩展。此外，使用网卡的存储器作为缓存，当数据存在于存储器上并且满足一定条件时，通过从该存储器向网络发送数据来减少主机上的负载。

2. 发明授权

US06327614B1 Network server device and file management system using cache associated with network interface processors for redirecting requested information between connection networks 失效
标题翻译：使用与网络接口处理器相关联的缓存的网络服务器设备和文件管理系统在连接网络之间重定向所请求的信息
公开(公告)号：US06327614B1
公开(公告)日：2001-12-04
申请号：US09154031
申请日：1998-09-16
申请人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
发明人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
IPC分类号： G06F15167
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/067 , H04L67/02 , H04L67/28 , H04L67/2814 , H04L67/2842 , H04L67/2895
摘要： A server device is formed by a plurality of network interface processors connected to a network, each network interface processor having a network interface local memory functioning as a cache memory for storing a part of server data and a network interface local processor, at least one storage interface processor connected with a storage device for storing the server data, and a connection network for connecting the network interface processors and the storage interface processor. In this server device, the network interface local processor of one network interface processor carries out a control processing such that a requested data stored In the network interface local memory of the one network Interface processor is transmitted to the network when a request received from the network at the one network interface processor satisfies a prescribed first condition, and the request is given to the storage interface processor via the connection network when the request satisfies a prescribed second condition and the requested data is transmitted to the network upon receiving the requested data returned from the storage interface processor to the one network interface processor via the connection network in response to the request.
摘要翻译：服务器设备由连接到网络的多个网络接口处理器形成，每个网络接口处理器具有用作存储服务器数据的一部分的高速缓存存储器的网络接口本地存储器和网络接口本地处理器，至少一个存储器与用于存储服务器数据的存储设备连接的接口处理器，以及用于连接网络接口处理器和存储接口处理器的连接网络。在该服务器装置中，一个网络接口处理器的网络接口本地处理器执行控制处理，使得当从网络接收到请求时，将存储在一个网络接口处理器的网络接口本地存储器中的所请求数据发送到网络在一个网络接口处理器满足规定的第一条件，并且当请求满足规定的第二条件时，经由连接网络将该请求提供给存储接口处理器，并且在接收到从所请求的数据返回时请求的数据被发送到网络所述存储接口处理器响应于所述请求经由所述连接网络连接到所述一个网络接口处理器。

3. 发明授权

US08812774B2 Memory system and computer program product 有权
标题翻译：内存系统和计算机程序产品
公开(公告)号：US08812774B2
公开(公告)日：2014-08-19
申请号：US13217461
申请日：2011-08-25
申请人： Shigehiro Asano , Shinichi Kanno , Kazuhiro Fukutomi , Akira Yamaga
发明人： Shigehiro Asano , Shinichi Kanno , Kazuhiro Fukutomi , Akira Yamaga
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1068
摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.
摘要翻译：根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子接收单元; 发电机组; 第二个表和书写单位。第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

4. 发明授权

US08612824B2 Semiconductor memory device and controlling method 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08612824B2
公开(公告)日：2013-12-17
申请号：US13038804
申请日：2011-03-02
申请人： Kazumasa Yamamoto , Shinichi Kanno , Shigehiro Asano , Hiroyuki Nagashima
发明人： Kazumasa Yamamoto , Shinichi Kanno , Shigehiro Asano , Hiroyuki Nagashima
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G11C16/3418 , G11C16/00 , G11C29/028
摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.
摘要翻译：半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。

5. 发明授权

US08397017B2 Controller and data storage device 有权
标题翻译：控制器和数据存储设备
公开(公告)号：US08397017B2
公开(公告)日：2013-03-12
申请号：US12723846
申请日：2010-03-15
申请人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
发明人： Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/064 , G06F3/0679 , G06F2212/7207
摘要： A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.
摘要翻译：易失性管理存储器存储用于管理存储介质的使用状态的管理信息。管理信息存储单元将管理信息分成多个分割片，并将它们分别存储在存储介质中。主控制器在存储分割片的同时从主机装置接收命令，根据存储各分割片之间的命令对存储介质执行数据处理，根据数据更新分割成分割片的管理信息处理内容，并创建表示管理信息的更新内容的日志。日志存储单元将日志存储在存储介质中。恢复单元将存储在存储介质中的分割信息作为管理信息读取到管理存储器，根据存储在存储介质中的日志更新管理信息，并恢复更新的管理信息。

6. 发明申请

US20120072811A1 CONTROLLER, STORAGE APPARATUS, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：控制器，存储设备和计算机程序产品
公开(公告)号：US20120072811A1
公开(公告)日：2012-03-22
申请号：US13035194
申请日：2011-02-25
申请人： Kazuhiro FUKUTOMI , Hiroshi Yao , Shinichi Kanno , Shigehiro Asano , Toshikatsu Hida , Yasuhiro Kimura
发明人： Kazuhiro FUKUTOMI , Hiroshi Yao , Shinichi Kanno , Shigehiro Asano , Toshikatsu Hida , Yasuhiro Kimura
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/108 , G06F2211/1059 , G06F2211/1073 , G06F2211/1092
摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.
摘要翻译：根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。第二数据存储单元存储用户数据和用户数据的奇偶校验数据。第一数据存储单元存储奇偶校验数据。控制器包括奇偶校验更新单元和奇偶校验写入单元。当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

7. 发明申请

US20120030528A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120030528A1
公开(公告)日：2012-02-02
申请号：US13270788
申请日：2011-10-11
申请人： Toshikatsu HIDA , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu HIDA , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G06F12/16 , G06F11/36
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
摘要翻译：作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

8. 发明授权

US07984325B2 Storage control device, data recovery device, and storage system 有权
标题翻译：存储控制装置，数据恢复装置和存储系统
公开(公告)号：US07984325B2
公开(公告)日：2011-07-19
申请号：US12398608
申请日：2009-03-05
申请人： Kazuhiro Fukutomi , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro Fukutomi , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
IPC分类号： G06F11/00
CPC分类号： G06F11/108 , G06F11/1068
摘要： When data in one semiconductor memory device is corrupted during a padding process by a padding unit and the data cannot be recovered even by using an error correcting code for correcting a data error, a storage control device issues a data recovery request to a data recovery device. The data recovery device reads the data from other semiconductor memory device in response to the data recovery request to recover the data, and returns a recovery result to the padding unit in the storage control device to perform the padding process.
摘要翻译：当一个半导体存储器件中的数据在填补单元的填充处理期间被破坏时，即使通过使用用于校正数据错误的纠错码也不能恢复数据，存储控制装置向数据恢复装置发出数据恢复请求。数据恢复装置响应于数据恢复请求从其他半导体存储装置读取数据以恢复数据，并将恢复结果返回到存储控制装置中的填充单元以执行填充处理。

9. 发明申请

US20100313084A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100313084A1
公开(公告)日：2010-12-09
申请号：US12529282
申请日：2008-09-22
申请人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
摘要翻译：作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

10. 发明申请

US20100223531A1 SEMICONDUCTOR STORAGE 失效
标题翻译：半导体存储
公开(公告)号：US20100223531A1
公开(公告)日：2010-09-02
申请号：US12713631
申请日：2010-02-26
申请人： Kazuhiro FUKUTOMI , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro FUKUTOMI , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
IPC分类号： H03M13/05 , G06F12/16 , G06F11/10
CPC分类号： G06F11/108 , G06F11/1052
摘要： A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated.
摘要翻译：半导体存储器包括被配置为从主机设备接收写请求的接收器; 存储单元，被配置为保存冗余数据生成/非生成信息; 写入单元，被配置为在半导体存储器阵列中写入数据，并将写入的数据的冗余数据生成/非生成信息写入存储单元中; 第一数据提取单元，被配置为从半导体存储器阵列保存的数据中提取不产生冗余数据的数据; 第一冗余数据生成单元，被配置为生成冗余数据; 第一冗余数据写入单元，被配置为将所生成的冗余数据写入所述半导体存储器阵列中; 以及第一冗余数据生成/非生成信息更新单元，被配置为更新由所述存储单元保持的冗余数据生成的数据的冗余数据生成/非生成信息。

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