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81. 发明授权

US07872299B2 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07872299B2
公开(公告)日：2011-01-18
申请号：US12081160
申请日：2008-04-11
申请人： Seok-Jun Won
发明人： Seok-Jun Won
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second regions having a lower density of charge-trap sites than the first region, and a gate electrode on the charge-trap insulation layer, wherein the first region is overlapped by the gate electrode and the second regions are outside of the first region.
摘要翻译：提供了非易失性存储器件及其制造方法，其可以防止或减少器件特性的劣化和击穿电压的劣化。非易失性存储器件可以包括半导体衬底，半导体衬底上的电荷阱绝缘层，并且具有第一区域和具有比第一区域更低的电荷陷阱位置密度的第二区域，阱绝缘层，其中第一区域与栅电极重叠，第二区域在第一区域的外部。

82. 发明申请

US20080218936A1 Analog capacitor 有权
标题翻译：模拟电容
公开(公告)号：US20080218936A1
公开(公告)日：2008-09-11
申请号：US12153306
申请日：2008-05-16
申请人： Seok-Jun Won , Yong-Kuk Jeong
发明人： Seok-Jun Won , Yong-Kuk Jeong
IPC分类号： H01G4/005
CPC分类号： H01L28/60
摘要： Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.
摘要翻译：模拟电容器及其制造方法包括具有下导电层的下电极，下导电层上的电容器电介质层和电容器电介质层上的与下电极相对的上电极，其中上电极电极包括至少与电容器介电层接触的上导电层，其中上导电层的电阻率高于下导电层的电阻率。

83. 发明授权

US07332404B2 Method of fabricating capacitor having metal electrode 失效
标题翻译：制造具有金属电极的电容器的方法
公开(公告)号：US07332404B2
公开(公告)日：2008-02-19
申请号：US11065988
申请日：2005-02-25
申请人： Seok-Jun Won
发明人： Seok-Jun Won
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/65 , H01L28/91
摘要： In a method of fabricating a capacitor, an interlayer insulating layer is formed on a semiconductor substrate. A contact plug penetrating the interlayer insulating layer is formed. An oxidation barrier layer and a molding layer are sequentially formed on the semiconductor substrate having the contact plug and the interlayer insulating layer. The molding layer is patterned to form a first lower electrode contact hole which exposes the oxidation barrier layer on the contact plug. An electrode layer pattern covering an inner sidewall of the first lower electrode contact hole is formed. The oxidation barrier layer exposed by the electrode layer pattern is etched to form a second lower electrode contact hole which exposes the contact plug. A conductive layer pattern covering an inner wall of the second lower electrode contact hole is then formed.
摘要翻译：在制造电容器的方法中，在半导体衬底上形成层间绝缘层。形成贯穿层间绝缘层的接触插塞。在具有接触插塞和层间绝缘层的半导体衬底上依次形成氧化阻隔层和成型层。模塑层被图案化以形成暴露接触插塞上的氧化阻挡层的第一下电极接触孔。形成覆盖第一下电极接触孔的内侧壁的电极层图案。蚀刻由电极层图案露出的氧化阻挡层，形成暴露接触插塞的第二下电极接触孔。然后形成覆盖第二下电极接触孔的内壁的导电层图案。

84. 发明授权

US07297591B2 Method for manufacturing capacitor of semiconductor device 有权
标题翻译：制造半导体器件电容器的方法
公开(公告)号：US07297591B2
公开(公告)日：2007-11-20
申请号：US10748308
申请日：2003-12-29
申请人： Seok-Jun Won , Myong-geun Yoon , Yong-Kuk Jeong , Dae-jin Kwon
发明人： Seok-Jun Won , Myong-geun Yoon , Yong-Kuk Jeong , Dae-jin Kwon
IPC分类号： H01L21/8242
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/02178 , H01L21/02337 , H01L21/3141 , H01L21/3143 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L28/65
摘要： Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.
摘要翻译：提供一种半导体器件的电容器。电容器包括设置在半导体衬底上的电容器下电极。包含氧化铝（Al 2 O 3 3）的第一电介质层设置在电容器下电极上。包括具有比氧化铝介电常数更高的介电常数的材料的第二电介质层设置在第一电介质层上。包含氧化铝的第三电介质层设置在第二电介质层上。电容器上电极设置在第三电介质层上。本发明的电容器可以改善电气性能。因此，可以降低功耗，并且每单位面积的电容足够高以实现高集成度。

85. 发明授权

US07294546B2 Capacitor for a semiconductor device and method of fabricating same 失效
标题翻译：一种用于半导体器件的电容器及其制造方法
公开(公告)号：US07294546B2
公开(公告)日：2007-11-13
申请号：US11519615
申请日：2006-09-12
申请人： Hong-Ki Kim , Ho-Kyu Kang , Moon-Han Park , Myong-Geun Yoon , Seok-Jun Won , Yong-Kuk Jeong , Kyung-Hun Kim
发明人： Hong-Ki Kim , Ho-Kyu Kang , Moon-Han Park , Myong-Geun Yoon , Seok-Jun Won , Yong-Kuk Jeong , Kyung-Hun Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
摘要翻译：电容器包括通过物理气相沉积和化学气相沉积形成的上电极。电容器的上电极可以包括通过化学气相沉积形成的第一上电极和通过物理气相沉积形成的第二上电极。或者，上电极可以包括通过物理气相沉积形成的第一上电极和通过化学气相沉积形成的第二上电极。电容器的上电极通过使用化学气相沉积和物理气相沉积的两个步骤形成。因此，可以使上部电极厚而快速地形成，从而不会劣化上部电极的电特性。

86. 发明授权

US07288453B2 Method of fabricating analog capacitor using post-treatment technique 有权
标题翻译：使用后处理技术制造模拟电容的方法
公开(公告)号：US07288453B2
公开(公告)日：2007-10-30
申请号：US11063942
申请日：2005-02-23
申请人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon
发明人： Yong-Kuk Jeong , Seok-Jun Won , Dae-Jin Kwon
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L21/02183 , H01L21/02323 , H01L21/0234 , H01L21/3105 , H01L21/3211
摘要： There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.
摘要翻译：提供了使用后处理技术制造模拟电容器的方法。该方法包括在半导体衬底上形成下绝缘层。底电极形成在下绝缘层上，电容器电介质层形成在底电极上。然后，将电容器电介质层在脱氧介质中进行后处理。然后，将后处理电容器电介质层在氧化介质中进行后处理。顶部电极形成在后处理电容器介电层上。通过如上所述的后处理制造的模拟电容具有低VCC。

87. 发明申请

US20070034988A1 Metal-Insulator-Metal (MIM) Capacitors Formed Beneath First Level Metallization and Methods of Forming Same 审中-公开
标题翻译：金属 - 绝缘体 - 金属（MIM）电容器形成于第一级金属化之前和形成方法相同
公开(公告)号：US20070034988A1
公开(公告)日：2007-02-15
申请号：US11457265
申请日：2006-07-13
申请人： Seok-Jun Won , Ju Kim , Min Song
发明人： Seok-Jun Won , Ju Kim , Min Song
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L23/5223 , H01L29/7833 , H01L2924/0002 , H01L2924/19015 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor for an integrated circuit may be provided on the interlayer insulating layer and covered by a inter-metal dielectric (IMD) layer. This IMD layer has at least a first opening therein that exposes an upper surface of a first electrode of the MIM capacitor. This first opening is filled with a first copper damascene interconnect pattern, which may in some embodiments be part of a dual-damascene copper interconnect structure associated with a first and lowermost level of metallization (e.g., M1 wiring layer). This first copper damascene interconnect pattern may have an upper surface that is planar with an upper surface of the IMD layer and a bottom surface that is in contact with the upper surface of the first electrode of the MIM capacitor.
摘要翻译：用于集成电路的金属 - 绝缘体 - 金属（MIM）电容器可以设置在层间绝缘层上并被金属间电介质（IMD）层覆盖。该IMD层至少具有暴露MIM电容器的第一电极的上表面的第一开口。该第一开口填充有第一铜镶嵌互连图案，其在一些实施例中可以是与第一和最下层金属化（例如，M1布线层）相关联的双镶嵌铜互连结构的一部分。该第一铜镶嵌互连图案可以具有与IMD层的上表面平坦的上表面和与MIM电容器的第一电极的上表面接触的底表面。

88. 发明申请

US20050272272A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050272272A1
公开(公告)日：2005-12-08
申请号：US11198541
申请日：2005-08-05
申请人： Jae-Hyun Yeo , Sung-Tae Kim , Young-Sun Kim , In-Sung Park , Seok-Jun Won , Yun-Jung Lee , Ki-Vin Im , Ki-Yeon Park
发明人： Jae-Hyun Yeo , Sung-Tae Kim , Young-Sun Kim , In-Sung Park , Seok-Jun Won , Yun-Jung Lee , Ki-Vin Im , Ki-Yeon Park
IPC分类号： H01L27/04 , H01L21/02 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/469 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/02271 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/02318 , H01L21/0234 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L28/40
摘要： A semiconductor device and a method for forming the same. A dielectric layer is formed on a semiconductor substrate or on a lower electrode of a capacitor. Vacuum annealing is performed on the dielectric layer. Thus, impurities remaining in the dielectric layer can be effectively removed, and the dielectric layer can be densified. As a result, the electrical characteristics of the semiconductor device are improved. For example, the leakage current characteristics of the dielectric layer are improved and capacitance is increased.
摘要翻译：一种半导体器件及其形成方法。电介质层形成在半导体衬底上或电容器的下电极上。在电介质层上进行真空退火。因此，可以有效地除去残留在电介质层中的杂质，并且可以使电介质层致密化。结果，提高了半导体器件的电特性。例如，介电层的漏电流特性得到改善，电容增大。

89. 发明授权

US06876029B2 Integrated circuit capacitors having doped HSG electrodes 失效
标题翻译：具有掺杂HSG电极的集成电路电容器
公开(公告)号：US06876029B2
公开(公告)日：2005-04-05
申请号：US10634244
申请日：2003-08-05
申请人： Seung-Hwan Lee , Sang-Hyeop Lee , Young-Sun Kim , Se-Jin Shim , You-Chan Jin , Ju-Tae Moon , Jin-Seok Choi , Young-Min Kim , Kyung-Hoon Kim , Kab-Jin Nam , Young-Wook Park , Seok-Jun Won , Young-Dae Kim
发明人： Seung-Hwan Lee , Sang-Hyeop Lee , Young-Sun Kim , Se-Jin Shim , You-Chan Jin , Ju-Tae Moon , Jin-Seok Choi , Young-Min Kim , Kyung-Hoon Kim , Kab-Jin Nam , Young-Wook Park , Seok-Jun Won , Young-Dae Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L29/92 , H01L27/108
CPC分类号： H01L28/84 , Y10S438/964
摘要： Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.
摘要翻译：形成集成电路电容器的方法包括以下步骤：通过在半导体衬底上形成导电层图案（例如，硅层）形成电容器的下电极，然后形成第一导电类型的半球形晶粒（HSG）硅表面层导电层图案。在导电层图案的外表面上包含HSG硅表面层增加给定横向尺寸的下电极的有效表面积。 HSG硅表面层还优选地充分掺杂有第一导电型掺杂剂（例如，N型），以使电容器反向偏置时可能在下电极中形成的任何耗尽层的尺寸最小化，从而提高电容器的特性 Cmin / Cmax比。扩散阻挡层（例如，氮化硅）也形成在下电极上，然后在扩散阻挡层上形成电介质层。扩散阻挡层优选由足够厚度的材料制成，以防止介电层和下电极之间的反应，并且还防止掺杂剂从HSG硅表面层向电介质层的扩散。电介质层还优选由具有高介电强度的材料形成以增加电容。

90. 发明授权

US06653155B2 Integrated circuit devices including a resistor pattern and methods for manufacturing the same 有权
标题翻译：包括电阻图案的集成电路器件及其制造方法
公开(公告)号：US06653155B2
公开(公告)日：2003-11-25
申请号：US10051908
申请日：2002-01-17
申请人： Seok-Jun Won , Young-Wook Park
发明人： Seok-Jun Won , Young-Wook Park
IPC分类号： H01L2100
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/10894
摘要： Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred &mgr;&OHgr;·cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.
摘要翻译：提供了用于形成包括具有所需电阻值的电阻图案的集成电路器件的方法。在集成电路基板上形成低电阻层。在与集成电路基板相对的低电阻层上形成绝缘层。在与低电阻层相反的绝缘层上形成可能具有至少约百μΩ·cm的电阻率的高电阻层。低电阻层，绝缘层和高电阻层在集成电路基板的区域中限定电阻器图案。还提供了包括由方法提供的电阻器图案的集成电路器件，并且还提供了用于形成与电阻器图案的金属触点的方法。

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