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81. 外观设计

USD544339S1 Fixture device 有权
标题翻译：夹具装置
公开(公告)号：USD544339S1
公开(公告)日：2007-06-12
申请号：US29229122
申请日：2005-05-03
申请人： Te-Ming Huang , Jason Chen
设计人： Te-Ming Huang , Jason Chen

82. 发明申请

US20070073655A1 Enhancing tables and SQL interaction with queue semantics 审中-公开
标题翻译：增强表和SQL与队列语义的交互
公开(公告)号：US20070073655A1
公开(公告)日：2007-03-29
申请号：US11238937
申请日：2005-09-29
申请人： Jason Chen , Ramesh Bhashyam
发明人： Jason Chen , Ramesh Bhashyam
IPC分类号： G06F17/30
CPC分类号： G06F16/24568
摘要： A database management system returns data from a database table in response to a database query. It does so by accessing an ordered list that indicates an order of retrieval for one or more rows in the database table and returning data from a row that is first in the order of retrieval before returning data from other rows. In some embodiments, after successfully returning the data, the row is deleted.
摘要翻译：数据库管理系统响应于数据库查询从数据库表返回数据。它通过访问指示数据库表中的一行或多行的检索顺序的顺序列表，并在从其他行返回数据之前从以检索顺序的第一行返回数据。在一些实施例中，在成功地返回数据之后，该行被删除。

83. 发明授权

US06938304B2 Multi-function clamp 失效
标题翻译：多功能夹
公开(公告)号：US06938304B2
公开(公告)日：2005-09-06
申请号：US10702559
申请日：2003-11-07
申请人： Jason Chen
发明人： Jason Chen
IPC分类号： A44B99/00 , A45F5/00 , A45F5/02 , B60R7/08 , A44B21/00
CPC分类号： B60R7/08 , A45F5/00 , A45F5/021 , A45F2200/0541 , A45F2200/0566 , Y10T24/1371 , Y10T24/1394
摘要： A multi-function clamp has a base plate, a connecting seat connected to the base plate, a pressing seat integrally formed with the connecting seat, an outer cover pivotally connected to the base plate and a rear clip securely engaged with the base plate. Multiple soft pads are securely sandwiched between the base plate and the outer cover to function as shock absorber. Spacers are formed on a rear face of the base plate to keep a distance to the rear clip. Hemispheres are formed on the rear clip to engage with the rear face of the base plate to clamp an object with the rear face of the base plate.
摘要翻译：多功能夹具具有基板，与基板连接的连接座，与连接座一体形成的按压座，可枢转地连接到基板的外盖和与基板牢固接合的后夹。多个软垫牢固地夹在基板和外盖之间，起减震作用。间隔件形成在基板的后表面上以保持与后夹子的距离。半球形成在后夹子上，以与基板的后表面接合，以夹住基板的后表面的物体。

84. 发明申请

US20050015530A1 MP3 voice recording/playing device 审中-公开
标题翻译： MP3录音/播放设备
公开(公告)号：US20050015530A1
公开(公告)日：2005-01-20
申请号：US10621748
申请日：2003-07-16
申请人： Potter Hsieh , Jason Chen
发明人： Potter Hsieh , Jason Chen
IPC分类号： G06F13/12 , G11C7/16
CPC分类号： G11C7/16 , G11C2207/16
摘要： The present invention provides a MP3 voice recording/playing device. Instead of comprising a memory module, the MP3 voice recording/playing device according to the present invention is connected to an external storage device so as to avoid the complicated process. The user has not to install the driver of the MP3 voice recording/playing device in the computer and has not to connect the MP3 voice recording/playing device to the computer via a transmission line in order to download the music. Therefore, the present invention can greatly reduce the cost and promote the efficiency.
摘要翻译：本发明提供一种MP3语音记录/播放装置。代替包括存储器模块，根据本发明的MP3语音记录/播放装置连接到外部存储装置，以避免复杂的处理。用户没有在计算机中安装MP3录音/播放设备的驱动程序，并且没有通过传输线将MP3语音记录/播放设备连接到计算机以便下载音乐。因此，本发明可以大大降低成本并提高效率。

85. 发明授权

US06603705B2 Method of allowing random access to rambus DRAM for short burst of data 有权
标题翻译：允许随机访问rambus DRAM用于短数据突发的方法
公开(公告)号：US06603705B2
公开(公告)日：2003-08-05
申请号：US09969597
申请日：2001-10-04
申请人： Jason Chen , Henry Chow , Mark William Janoska
发明人： Jason Chen , Henry Chow , Mark William Janoska
IPC分类号： G11C818
CPC分类号： G11C7/1072 , G11C8/12
摘要： Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size. Within each frame, the read addresses to be accessed by read memory operations can be rearranged to minimize memory bank access conflicts with either write addresses to be accessed by write memory operations or other read addresses.
摘要翻译：用于布置存储器访问操作以最小化这些操作之间的存储器组冲突的方法和设备。实现存储器访问操作的固定模式以最小化读取存储器访问操作和写入存储器访问操作之间的转换的影响。写存储器访问操作的后跟读存储器访问操作然后在不进行存储器访问操作时跟随设置的间隙的写 - 读 - 间隙（WRG）设置模式满足RDRAM的特定要求。在WRG模式中，选择读地址和写地址以最小化存储器存取冲突。通过定义特定数量的WRG模式的重复的集合帧大小来辅助这种选择来提高存储器访问操作的效率。然后将所有存储器存取操作重新排列以符合WRG模式，并且WRG模式的重复被划分成具有等于所定义的帧大小的大小的帧。在每个帧内，通过读取存储器操作访问的读取地址可以被重新排列，以使存储器组访问冲突与通过写入存储器操作或其它读取地址访问的写入地址最小化。

86. 发明授权

US06526536B1 Apparatus within an integrated circuit for preventing the integrated circuit from erroneously entering a test mode operation 失效
标题翻译：集成电路内的装置，用于防止集成电路错误地进入测试模式操作
公开(公告)号：US06526536B1
公开(公告)日：2003-02-25
申请号：US08843786
申请日：1997-04-21
申请人： Jason Chen , Bao-Shiang Sun , Henry Fan
发明人： Jason Chen , Bao-Shiang Sun , Henry Fan
IPC分类号： G06F1100
CPC分类号： G01R31/31701 , G06F11/0751
摘要： An integrated circuit is disclosed which includes a start test mode circuit for generating a test mode start-up signal to cause the integrated circuit to enter a test mode, and an automatic reset circuit responsive to the test mode start-up signal for preventing the integrated circuit from erroneously entering a test mode during normal operation.
摘要翻译：公开了一种集成电路，其包括用于产生测试模式启动信号以使集成电路进入测试模式的启动测试模式电路，以及响应于测试模式启动信号的自动复位电路，用于防止集成在正常操作期间错误地进入测试模式的电路。

87. 发明授权

US6011443A CMOS voltage controlled oscillator 失效
标题翻译： CMOS压控振荡器
公开(公告)号：US6011443A
公开(公告)日：2000-01-04
申请号：US116646
申请日：1998-07-16
申请人： Jason Chen , Ping Xu
发明人： Jason Chen , Ping Xu
IPC分类号： H03B5/20 , H03K3/03 , H03K3/354 , H03B5/24
CPC分类号： H03K3/03 , H03K3/354
摘要： A CMOS voltage controlled oscillator (VCO) having an improved voltage-to-current converter and an active MOS load operating in the triode region to provide improved performance characteristics including a small differential logic swing and a high frequency output. The voltage-to-current converter of the CMOS VCO comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1
摘要翻译：具有改进的电压 - 电流转换器和在三极管区域中工作的有源MOS负载的CMOS压控振荡器（VCO），以提供改进的性能特性，包括小的差分逻辑摆幅和高频输出。 CMOS VCO的电压 - 电流转换器包括一对MOS晶体管，其中一个具有纵横比（WP / LP），另一个具有纵横比（WP / LP）/ n，其中1 < n <4。该配置使得电压 - 电流转换器中的第三MOS晶体管仅在三极管区域中工作。 CMOS VCO还包括具有以环形配置连接的多个延迟级的ICO部分。每个延迟级包括一对输入MOS晶体管和一对负载MOS晶体管。根据本发明，电压 - 电流转换器使每个负载MOS晶体管在三极管区域中工作。

88. 发明授权

US5977893A Method for testing charge redistribution type digital-to-analog and analog-to-digital converters 失效
标题翻译：用于测试电荷再分配型数模转换器和模数转换器的方法
公开(公告)号：US5977893A
公开(公告)日：1999-11-02
申请号：US844170
申请日：1997-04-18
申请人： Jason Chen , Henry Fan
发明人： Jason Chen , Henry Fan
IPC分类号： G01R31/3167 , H03M1/10 , H03M1/80
CPC分类号： H03M1/1071 , G01R31/3167 , H03M1/804
摘要： A test method for charge redistribution type digital-to-analog and analog-to-digital converters by utilizing the special characteristics of a DAC or ADC such that the accuracy and linearity of the converted signal is only determined by the internal capacitance ratios of the converter, and that the accuracy and linearity are not related to the test reference voltage, the test voltage and the noise signal of the test machine. The test method utilizes a principle of capacitance comparison to directly compare the capacitance ratios in a converter in order to determine the accuracy and linearity of the converted signal. The present invention method enables an effective reduction in the test time and test steps required and an increase in the test efficiency.
摘要翻译：通过利用DAC或ADC的特殊特性，电荷再分配型数模转换器和模数转换器的测试方法，使得转换信号的精度和线性度仅由转换器的内部电容比决定精度和线性度与试验机的试验参考电压，试验电压和噪声信号无关。测试方法利用电容比较原理直接比较转换器中的电容比，以确定转换信号的精度和线性。本发明的方法能够有效地减少测试时间和所需的测试步骤并提高测试效率。

89. 发明授权

US5745541A Data shift control circuit 失效
标题翻译：数据移位控制电路
公开(公告)号：US5745541A
公开(公告)日：1998-04-28
申请号：US797006
申请日：1997-02-07
申请人： Yi Lin , Jason Chen , Henry Fan
发明人： Yi Lin , Jason Chen , Henry Fan
IPC分类号： G11C19/00
CPC分类号： G11C19/00
摘要： A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.
摘要翻译：公开了一种用于响应逻辑运算命令码的移位寄存器的数据移位控制电路。移位寄存器包括第一寄存器和第二寄存器，逻辑运算命令代码包括第一部分和第二部分。电路包括用于解码第一部分以传送移动信号的第一解码器; 第二解码器，用于解码所述第二部分以发送控制信号; 电连接到第一寄存器和第二寄存器的控制信号通道，用于允许第一寄存器和第二寄存器接收控制信号并允许移位寄存器执行第一动作; 以及移动信号通道，电连接到移位寄存器的所有寄存器，用于允许所有寄存器接收移动信号并允许移位寄存器执行第二动作。

90. 外观设计

USD392057S Halogen lamp 失效
公开(公告)号：USD392057S
公开(公告)日：1998-03-10
申请号：US71583
申请日：1997-05-30
申请人： Jason Chen
设计人： Jason Chen

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