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81. 发明专利

NZ585421A An apparatus for encoding using a low-density parity check code 未知
公开(公告)号：NZ585421A
公开(公告)日：2013-03-28
申请号：NZ58542108
申请日：2008-11-18
申请人： SONY CORP
发明人： YOKOKAWA TAKASHI , YAMAMOTO MAKIKO , OKADA SATOSHI , IKEGAYA RYOJI
IPC分类号： H03M13/19 , H04L1/00 , H04L27/34 , H04L27/36
摘要： Disclosed is an encoding apparatus for carrying out encoding by an LDPC (Low Density Parity Check) code. The apparatus is comprised of encoding means and a parity check matrix. The encoding means is configured for carrying out encoding by an LDPC code which has a code length of 64,800 bits and an encoding rate of 2/3. The parity check matrix of the LDPC code is configured such that elements of the value 1 of an information matrix are arranged in a period of every 360 columns in the column direction. The information matrix corresponds to the code length of the parity check matrix and an information length corresponding to the encoding rate, decided by a parity check matrix initial value table representative of the positions of the elements of the value 1 of the information matrix.

82. 发明专利

AU2008330716B8 Data processing device, data processing method, coding device and coding method 未知
公开(公告)号：AU2008330716B8
公开(公告)日：2013-01-24
申请号：AU2008330716
申请日：2008-11-25
申请人： SONY CORP
发明人： YAMAMOTO MAKIKO , IKEGAYA RYOJI , YOKOKAWA TAKASHI , OKADA SATOSHI
IPC分类号： H03M13/19
摘要： The present invention is related to a data processing device, a data processing method, a coding device and a coding method that can be configured to improve a tolerance to an error. A code bit of mb bits in an LDPC code having a code length of 64,800 bits and a code rate of 2/3 as prescribed in the DVB-S.2 is replaced and a code bit after the replacement is a symbol bit with b symbols. When m is 8 and b is 2, and code bits with 8x2 bits and (i+1)th bit from the most significant bit of the 8x2 symbol bits of successive two symbols are expressed by bi and yi, respectively, the following replacement for each allocation is carried out: b0 with y15, b1 with y7, b2 with y1, b3 with y5, b4 with y6, b5 with y13, b6 with y11, b7 with y9, b8 with y8, b9 with y14, b10 with y12, b11 with y3, b12 with y0, b13 with y10, b14 with y4, and b15 with y2. The present invention can be applied to a transmission system to transmit the LDPC code, for instance.

83. 发明专利

ZA201003477B Data processing device, data processing method, coding device and coding method 未知
公开(公告)号：ZA201003477B
公开(公告)日：2010-09-29
申请号：ZA201003477
申请日：2010-05-17
申请人： SONY CORP
发明人： YOKOKAWA TAKASHI , YAMAMOTO MAKIKO , OKADA SATOSHI , IKEGAYA RYOJI
IPC分类号： H03M20060101

84. 发明专利

AU2008330816A2 Data process device, data process method, coding device, coding method 未知
公开(公告)号：AU2008330816A2
公开(公告)日：2010-07-22
申请号：AU2008330816
申请日：2008-11-18
申请人： SONY CORP
发明人： YAMAMOTO MAKIKO , OKADA SATOSHI , YOKOKAWA TAKASHI , IKEGAYA RYOJI
IPC分类号： H03M13/19
摘要： The invention relates to a data processing apparatus (12) for the reception of LDPC encoded signals. At the transmitter, after encoding information bits with an LDPC code prescribed in the DVB-S.2 specification and having a code length of 64,800 and an encoding rate of 2/3 (21), there is a demultiplexer (25) allocating mb code bits to mb symbol bits. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8 × 2 code bits and 8 × 2 symbol bits of two successive 256QAM symbols are represented by b i and y i , respectively, the multiplexer is allocating b 0 to y 15 , b 1 to y 7 , b 2 to y 1 , b 3 to y 5 , b 4 to y 6 , b 5 to y 13 , b 6 to y 11 , b 7 to y 9 , b 8 to y 8 , b 9 to y 14 , b 10 to y 12 , b 11 to y 3 , b 12 to y 0 , b 13 to y 10 , b 14 to y 4 and b 15 to y 2 . The reception apparatus (12) comprises the corresponding multiplexer (54) and an LDPC decoding section (56). The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.

85. 发明专利

AU2008330672A1 Data processing device and data processing method 未知
公开(公告)号：AU2008330672A1
公开(公告)日：2009-06-04
申请号：AU2008330672
申请日：2008-11-26
申请人： SONY CORP
发明人： OKADA SATOSHI , YAMAMOTO MAKIKO , IKEGAYA RYOJI , YOKOKAWA TAKASHI
IPC分类号： H03M13/19
摘要： The present application relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer (25) replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12 × 1 code bits and the 12 × 1 symbol bits of one symbol are represented as bits b i and y i , replacement for allocating, for example, b 0 to y 8 , b 1 to y 0 , b 2 to y 6 , b 3 to y 1 , b 4 to y 4 , b 5 to y 5 , b 6 to y 2 , b 7 to y 3 , b 8 to y 7 , b 9 to y 10 , b 10 to y 11 and b 11 to y 9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth as specified in the DVB framework. At the receiving end, a reception apparatus (12) comprises a deinterleaver (53) including a multiplexer (54), wherein a reverse replacement means (1001) reverses the above described allocation and writes the thus obtained code bits into a memory (1002).

86. 发明专利

JP2011171879A Receiving apparatus, information processing method and program 有权
标题翻译：接收设备，信息处理方法和程序
公开(公告)号：JP2011171879A
公开(公告)日：2011-09-01
申请号：JP2010032125
申请日：2010-02-17
申请人： Sony Corp , ソニー株式会社
发明人： IKEDA TAMOTSU , SHIMURA RYUICHIRO , OKAMOTO TAKUYA , OKADA SATOSHI
IPC分类号： H04N7/16
CPC分类号： G08B27/008 , G08B21/10 , G08B25/007 , H04L1/0045 , H04L1/0057
摘要： PROBLEM TO BE SOLVED: To quickly cope with a situation in which alarm information is transmitted. SOLUTION: In ISDB-T standard, earthquake motion warning information is transmitted by an AC (auxiliary channel) signal. Before receiving the 204-th bit which is the final bit composing the AC signal, a receiving part 12 determines whether the earthquake motion warning information is transmitted at the timing of receiving up to predetermined bits. For instance, when bits from the second bit up to the fourth bit of the AC signal is received and the configuration identification of the three received bits are 001 or 110, the receiving part determines that the earthquake motion warning information is transmitted. Then, a quick detection flag is output from the receiving part 12, and a controller 16 receiving the quick detection flag starts processing for notifying a user of information concerned with earthquake. This invention can be applied to a receiving apparatus for receiving digital broadcasting. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：快速应对发送报警信息的情况。解决方案：在ISDB-T标准中，通过AC（辅助通道）信号发送地震运动警告信息。在接收到构成AC信号的最终位的第204位之前，接收部分12确定在接收到预定位的定时是否发送地震运动警告信息。例如，当接收到来自AC信号的第二位到第四位的位并且三个接收位的配置标识为001或110时，接收部分确定发送了地震运动警告信息。然后，从接收部12输出快速检测标志，接收快速检测标志的控制器16开始处理，通知用户有关地震的信息。本发明可以应用于接收数字广播的接收装置。版权所有（C）2011，JPO＆INPIT

87. 发明专利

JP2011142421A Reception apparatus and method, program and reception system 有权
标题翻译：接收装置和方法，程序和接收系统
公开(公告)号：JP2011142421A
公开(公告)日：2011-07-21
申请号：JP2010000919
申请日：2010-01-06
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , OKADA SATOSHI
IPC分类号： H04J11/00
CPC分类号： H04L27/2647 , H04H40/18 , H04H60/40 , H04N21/235 , H04N21/23608 , H04N21/2383 , H04N21/242 , H04N21/4302 , H04N21/4305 , H04N21/434 , H04N21/4344 , H04N21/4345 , H04N21/435 , H04N21/4382 , H04W56/00 , H04W56/001 , H04W56/003
摘要： PROBLEM TO BE SOLVED: To provide a reception apparatus for reliably obtaining re-synchronism. SOLUTION: The reception apparatus includes: a time lag detection section 51 configured to count a relative time by an ISCR counter 51A, which is obtained by successively adding packet rates P ts with respect to a reference time indicated by an ISCR to be reference among the ISCRs added to TS packets concerning the TS packets of Common PLP and Data PLP to be read from a buffer 31, compare the counted relative time with an additional time indicated by the ISCR temporally after the ISCR to be reference, and detect the time lag; and a time lag correction section 52 configured to correct a displacement in the time direction between the Common PLP and Data PLP stored in the buffer 31, based on the detection result by the time lag detection section 51. Thus, the re-synchronism is reliably obtained even in out-of-synchronism between the Common PLP and Data PLP. The invention is applied to the reception apparatus for receiving a signal by an M-PLP system in DVB-T.2. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供可靠地获得再同步的接收装置。解决方案：接收装置包括：时间延迟检测部分51，被配置为通过相对于引用连续添加分组比率P ts 而获得的ISCR计数器51A对相对时间进行计数由ISCR指示的时间指示在添加到关于要从缓冲器31读取的公共PLP和数据PLP的TS分组的TS分组上的IS分组之间的参考，将计数的相对时间与在ISCR之后临时地由ISCR指示的附加时间进行比较作为参考，并检测时滞; 以及时间差校正部52，其被配置为基于时间延迟检测部51的检测结果来校正存储在缓冲器31中的公共PLP和数据PLP之间的时间方向上的位移。因此，重新同步是可靠的即使在Common PLP和Data PLP之间的不同步中也获得了该功能。本发明适用于DVB-T.2中的M-PLP系统接收信号的接收装置。版权所有（C）2011，JPO＆INPIT

88. 发明专利

JP2009225416A Data processing apparatus, and data processing method 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：JP2009225416A
公开(公告)日：2009-10-01
申请号：JP2008176910
申请日：2008-07-07
申请人： Sony Corp , ソニー株式会社
发明人： OKADA SATOSHI , SAKAI RUI , YOKOGAWA MINESHI , YAMAMOTO MAKIKO
IPC分类号： H03M13/19 , H03M13/25 , H04L27/34
摘要： PROBLEM TO BE SOLVED: To improve data immunity to error. SOLUTION: A demultiplexer 25 switches code bits of mb bits, in accordance with allocation rules for allocating code bits of LDPC codes to symbol bits representing a symbol, and defines the switched code bits as symbol bits for (b) pieces of symbols. For example, when (m) is 4 and (b) is 2, an (i+1)th bit from a most significant bit in the code bits of 4×2 bits is defined as a bit b i , and an (i+1)th bit from the most significant bit in the symbol bits of 4×2 bits for continuous two symbols is defined as a bit y i . Then, switching is performed to allocate b 0 to y 0 , b 1 to y 1 , b 2 to y 4 , b 3 to y 2 , b 4 to y 3 , b 5 to y 5 , b 6 to y 6 , and b 7 to y 7 . For example, the present invention may be applicable to a transmission system for transmitting LDPC codes, or the like. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高数据免除错误。解决方案：解复用器25根据用于将LDPC码的码位分配给代表符号的符号位的分配规则来切换mb位的码位，并将切换的码位定义为（b）符号的符号位。例如，当（m）为4且（b）为2时，在4×2比特的码比特中，来自最高有效位的第（i + 1）比特被定义为比特b < SB>和连续两个符号的4×2位的符号位中最高有效位的第（i + 1）位被定义为位y i 。然后，执行切换以将y 0 ，b 1 的b 0 分配给y 1 ，b SB > 2 至y 4 ，b 3 至y 2 ，b 4 至y 7 至y 7 。例如，本发明可以适用于用于发送LDPC码的传输系统等。版权所有（C）2010，JPO＆INPIT

89. 发明专利

JP2009225325A Decoding method and decoding apparatus, and program 审中-公开
标题翻译：解码方法和解码设备及程序
公开(公告)号：JP2009225325A
公开(公告)日：2009-10-01
申请号：JP2008070013
申请日：2008-03-18
申请人： Sony Corp , ソニー株式会社
发明人： MIYAUCHI TOSHIYUKI , YAMAMOTO MAKIKO , OKADA SATOSHI
IPC分类号： H03M13/37
摘要： PROBLEM TO BE SOLVED: To provide a decoding method and decoding apparatus capable of reducing a bit error rate, and to provide a program.
SOLUTION: The invention relates to a decoding apparatus 30 wherein reception words are sorted in accordance with the magnitude of belief, the belief is updated by performing belief propagation (BP) using a parity check matrix made diagonal in the order of reception words, and the operation is repeated again for the updated value. In a case where a posteriori probability is below a certain fixed value, the decoded word is not used.
COPYRIGHT: (C)2010,JPO&INPIT

90. 发明专利

JP2009100422A Receiving apparatus and method, and program 有权
标题翻译：接收装置和方法，程序
公开(公告)号：JP2009100422A
公开(公告)日：2009-05-07
申请号：JP2007272518
申请日：2007-10-19
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , OKADA SATOSHI , SHINTANI OSAMU
IPC分类号： H03M13/19 , H04L1/00 , H04N19/89
CPC分类号： H03M13/11 , H04L1/0052 , H04L1/0057 , H04L1/007
摘要： PROBLEM TO BE SOLVED: To provide a receiving apparatus applicable to a system for multiplexing an LDPC-coded data signal and a TMCC signal and transmitting the multiplexed signal. SOLUTION: A transmission signal is separated into an LDPC-coded data signal and a TMCC signal in a separation part 1501 and the LDPC-coded data signal and the TMCC signal are respectively stored in a data signal input buffer 1502D and a TMCC signal input buffer 1502T. A control part 1506 selects either one of the data signal stored in the data signal input buffer 1502D and the TMCC signal stored in the TMCC signal input buffer 1502T as a signal to be decoded and transfers the selected signal to an LDPC decoding part 1504 through a selector 1503 to execute control for decoding the signal to be decoded. This invention can be applied to an LDPC decoding apparatus. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种适用于复用LDPC编码数据信号和TMCC信号的系统的接收装置，并发送多路复用信号。解决方案：在分离部分1501中将传输信号分离为LDPC编码数据信号和TMCC信号，并将LDPC编码数据信号和TMCC信号分别存储在数据信号输入缓冲器1502D和TMCC中信号输入缓冲器1502T。控制部分1506选择存储在数据信号输入缓冲器1502D中的数据信号中的任何一个和存储在TMCC信号输入缓冲器1502T中的TMCC信号作为要解码的信号，并将所选择的信号传送到LDPC解码部分1504，通过选择器1503执行用于对要解码的信号进行解码的控制。本发明可以应用于LDPC解码装置。版权所有（C）2009，JPO＆INPIT

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