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    • 86. 发明专利
    • AT531048T
    • 2011-11-15
    • AT07783139
    • 2007-05-02
    • SANDISK CORP
    • LI YAN
    • G11C16/26G11C7/22G11C11/56
    • Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A scheme for caching read data is implemented so that even when the read for a current page on a current wordline must be preceded by a prerequisite read of data on an adjacent wordline, the prerequisite read along with any I/O access is preemptively done in the cycle for reading a previous page so that the current read can be performed while the previously read page is busy with the I/O access.
    • 88. 发明专利
    • AT475185T
    • 2010-08-15
    • AT05852349
    • 2005-11-28
    • SANDISK CORP
    • GOROBETS SERGEY ANATOLIEVICHLI YAN
    • G11C16/10G11C7/10
    • A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be freed up for other data or even eliminated, reducing the amount of controller space that needs to devoted data buffering. In exemplary embodiments, the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data. The exemplary embodiments are for memory cells storing multi-state data, both in the format of independent upper page, lower page form, as well as in 2-bit form. This can be accomplished by a state machine and data latches in the sense amp area on the memory, without use of the controller.
    • 89. 发明专利
    • AT459962T
    • 2010-03-15
    • AT05747864
    • 2005-05-10
    • SANDISK CORP
    • LI YANLEE SEUNGPILCHAN SIU LUNG
    • G11C11/56
    • A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by pre-emptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
    • 90. 发明专利
    • AT458248T
    • 2010-03-15
    • AT06739812
    • 2006-03-27
    • SANDISK CORP
    • LI YANYERO EMILIO
    • G11C7/00G11C16/10
    • Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.