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1. 发明专利

JP2005129194A Programming based on behavior of nonvolatile memory 有权
标题翻译：基于非易失性存储器行为的编程
公开(公告)号：JP2005129194A
公开(公告)日：2005-05-19
申请号：JP2004076471
申请日：2004-03-17
申请人： Sandisk Corp , Toshiba Corp , サンディスクコーポレイションSanDisk Corporation , 株式会社東芝
发明人： CHEN JIAN , LUTZE JEFFREY W , LI YAN , GUTERMAN DANIEL C , TANAKA TOMOHARU
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： PROBLEM TO BE SOLVED: To improve the process of programming a set of memory cells by adjusting programming processing, based on the behavior of the memory cell. SOLUTION: For example, a set of program pulses are applied to word lines for a set of flash memory cells. Determination is made as to a memory cell to be easily programmed and a memory cell to be difficult to be programmed. Based on the determination as to the memory cell to be programmed easily and the program to be difficult to be programmed, a bit-line voltage (or other parameters) are adjusted. Then, programming processing is continued by the adjusted bit-line voltage (or other parameters). COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：基于存储器单元的行为，通过调整编程处理来改进对一组存储器单元的编程过程。
解决方案：例如，一组编程脉冲被施加到一组闪存单元的字线。确定要容易编程的存储器单元和难以编程的存储器单元。基于对容易编程的存储器单元的确定以及难以编程的程序，调整位线电压（或其他参数）。然后，通过调整的位线电压（或其他参数）继续编程处理。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005150707A Method for discriminating non-volatile memory element by inadequate subthreshold value gradient or weak transconductance 有权
标题翻译：通过不准确的子带值梯度或弱交叉判断非易失性存储元件的方法
公开(公告)号：JP2005150707A
公开(公告)日：2005-06-09
申请号：JP2004304919
申请日：2004-09-17
申请人： Sandisk Corp , Toshiba Corp , サンディスクコーポレイションSanDisk Corporation , 株式会社東芝
发明人： CHEN JIAN , KANEBAKO KAZUNORI , LUTZE JEFFREY W , LI YAN , TANAKA TOMOHARU
IPC分类号： G01R31/28 , G11C16/02 , G11C16/04 , G11C16/34 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C29/00
CPC分类号： G11C16/3495 , G11C16/04 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： PROBLEM TO BE SOLVED: To provide a method for discriminating cells which have inadequate subthreshold values and weak transconductances.
SOLUTION: A first group technique focuses the lens on inadequate subthreshold value behaviors of deteriorated memory elements by carrying out cycle operation of the cells, then programming them to a potential higher than earth potential, and then reading the cells with a control gate voltage lower than a threshold voltage for the potential in order to see whether the cells are conducted. A second group practice form focuses the lens on weak transconductance behaviors by reading the programmed cells with a control gate voltage higher enough than the threshold voltage. In a third group practice form, voltage level in source-drain regions of the memory elements is varied. While current vs. voltage curves of good memory elements are rather stable under such a shift in bias condition, current vs. voltage curves of the deteriorated memory elements show bigger shifts. Thereby the discrimination between the good memory element group and the failure memory element group becomes possible.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于区分具有不足的亚阈值和弱跨导的单元的方法。解决方案：第一组技术通过执行单元的循环操作，将透镜聚焦在劣化的存储元件的不足的亚阈值行为上，然后将其编程为比地电位高的电位，然后用控制栅极读取单元电压低于电位的阈值电压，以查看电池是否导通。第二组实践形式通过用比阈值电压足够高的控制栅极电压读取编程单元，将透镜集中在弱跨导行为上。在第三组练习形式中，存储元件的源极 - 漏极区域中的电压电平是变化的。虽然良好的存储器元件的电流与电压曲线在偏置条件的这种偏移下相当稳定，但是劣化的存储元件的电流与电压曲线显示出更大的偏移。由此，良好的存储元件组与故障存储元件组之间的辨别成为可能。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004030866A Processing technique to reduce program interference and reading interference of nonvolatile memory 有权
公开(公告)号：JP2004030866A
公开(公告)日：2004-01-29
申请号：JP2003051038
申请日：2003-02-27
申请人： Sandisk Corp , サンディスクコーポレイションSanDisk Corporation
发明人： LI YAN , CHEN JIAN , CERNEA RAUL-ADRIAN
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/3418
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory that is provided with a plurality of erasing units or blocks, in which a reading and a programming are independently conducted, while each block is divided into a plurality of portions that commonly utilize the same word lines in order to save a row decoding region in a conventional technique.
SOLUTION: A flush EEPROM (electrically erasable and programable ROM) having a NAND architechture which is provided with a block being constituted of left and right one sided portions is a good example of embodiment. In this case, a standard page (a data transfer unit) size having equal to or more than one and consisting of 512 bite data is stored. In the above example, each of the left and the right portions of one block is provided with an independent source line, source lines having an independent set and a drain selection line. As an example, during a left side programming or a reading, a bias is applied to the right side to form a boosting channel to reduce data interference. In a different set embodiment configuration, the portions may be provided with independent well structures.
COPYRIGHT: (C)2004,JPO

4. 发明申请

WO2007131059A3 NON-VOLATILE MEMORY WITH BACKGROUND DATA LATCH CACHING DURING ERASE OPERATIONS AND METHODS THEREFOR 审中-公开
标题翻译：具有背景数据的非易失性存储器在擦除操作期间进行缓存及其方法
公开(公告)号：WO2007131059A3
公开(公告)日：2008-03-13
申请号：PCT/US2007068065
申请日：2007-05-02
申请人： SANDISK CORP , LIN JASON , LI YAN
发明人： LIN JASON , LI YAN
IPC分类号： G11C16/10 , G11C7/10 , G11C16/32
CPC分类号： G11C7/1015 , G06F12/0866 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C16/10 , G11C16/32
摘要： Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.
摘要翻译：来自存储器读或写操作的部分延迟是通过I / O总线将数据输入或从存储器的数据锁存器输出。存在用于通过允许存储器在存储器内核正在进行擦除操作的情况下在后台执行这些数据高速缓存和传送操作中的一些来提高非易失性存储器件中的性能的方法和电路。在示例性实施例中，在擦除操作之前插入读取操作，或者在擦除操作的软编程阶段插入一个或多个读取操作。以这种方式，可以在擦除操作发生时输出读取的数据，从而利用另外的等待时间。

5. 发明申请

WO2004029984A3 NON-VOLATILE MEMORY AND ITS SENSING METHOD 审中-公开
标题翻译：非易失性存储器及其感测方法
公开(公告)号：WO2004029984A3
公开(公告)日：2004-12-23
申请号：PCT/US0329603
申请日：2003-09-23
申请人： SANDISK CORP
发明人： CERNEA RAUL-ADRIAN , LI YAN
IPC分类号： G11C7/00 , G11C7/06 , G11C11/56 , G11C16/26 , G11C16/28
CPC分类号： G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/26
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的控制栅极电压被跨过电阻的电压降错误地偏置。当通过接地回路的电流减小时，该误差被最小化。用于减少源极偏置的方法是通过具有用于多通感测的特征和技术的读/写电路实现的。当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。以这种方式，关闭操作不会影响感测操作。在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

6. 发明申请

WO2009035834A3 NONVOLATILE MEMORY AND METHOD FOR ON-CHIP PSEUDO-RANDOMIZATION OF DATA WITHIN A PAGE AND BETWEEN PAGES 审中-公开
标题翻译：非页面存储器和方法，用于在页面和页面之间的数据的片上PSEUDO-RANDOMIZATION
公开(公告)号：WO2009035834A3
公开(公告)日：2009-05-22
申请号：PCT/US2008073750
申请日：2008-08-20
申请人： SANDISK CORP , LI YAN , FONG YUPIN KAWING , MOKHLESI NIMA
发明人： LI YAN , FONG YUPIN KAWING , MOKHLESI NIMA
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C7/1006 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/5647
摘要： Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.
摘要翻译：集成电路存储芯片内的特征使得能够对存储在非易失性存储单元阵列中的数据进行加扰或随机化。在一个实施例中，每个页面内的随机化有助于控制感测期间的源负载误差和在相邻小区之间的浮动栅极到浮动栅极耦合。从页面到页面的随机化有助于减少程序干扰，用户读取干扰以及由特定数据模式的重复和长期存储引起的浮动栅极耦合的浮动栅极。在另一个实施例中，在页面之间和页面之间实现随机化。在不同的实施例中，加扰或随机化可以是预定的，或代码生成的伪随机化或用户驱动的随机化。这些功能在集成电路存储芯片的有限资源和预算内完成。

7. 发明申请

WO2007130976A2 NON-VOLATILE MEMORY WITH BACKGROUND DATA LATCH CACHING DURING PROGRAM OPERATIONS AND METHODS THEREFOR 审中-公开
标题翻译：具有背景数据的非易失性存储器在程序运行期间进行缓存及其方法
公开(公告)号：WO2007130976A2
公开(公告)日：2007-11-15
申请号：PCT/US2007067930
申请日：2007-05-01
申请人： SANDISK CORP , LI YAN
发明人： LI YAN
IPC分类号： G11C16/10 , G11C7/10
CPC分类号： G11C7/1015 , G06F12/0893 , G06F2212/2022 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5643
摘要： Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a write operation. In the exemplary embodiment, when the multiple phases of a write operation vary as to the number of states to track, a phase-dependent coding enables efficient utilization of the available data latches, thereby allowing a maximum of surplus latches for background cache operations.
摘要翻译：来自存储器读或写操作的部分延迟是通过I / O总线将数据输入或从存储器的数据锁存器输出。存在用于通过允许存储器在存储器核心忙于写入操作的情况下在后台执行这些数据高速缓存和传送操作中的一些来提高非易失性存储器件中的性能的方法和电路。在示例性实施例中，当写入操作的多个相位对于要跟踪的状态的数量而言变化时，相位相关编码使得能够有效利用可用的数据锁存器，从而允许用于后台高速缓存操作的多余的锁存器的最大值。

8. 发明申请

WO2007131127A8 MERGING QUEUED MEMORY OPERATION IN A NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中合并存储器操作
公开(公告)号：WO2007131127A8
公开(公告)日：2008-06-05
申请号：PCT/US2007068172
申请日：2007-05-03
申请人： SANDISK CORP , LI YAN
发明人： LI YAN
IPC分类号： G11C16/12 , G11C11/56
CPC分类号： G06F12/0893 , G06F2212/2022 , G06F2212/3042 , G11C7/22 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C2207/2245 , G11C2211/5643
摘要： Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.
摘要翻译：存在用于执行当前存储器操作而其他多个挂起存储器操作排队的方法和电路。此外，当某些条件得到满足时，这些内存操作中的一些可组合或合并以提高效率和其他好处。多个存储器操作的管理通过提供由存储器操作队列管理器控制的存储器操作队列来实现。存储器操作队列管理器优选地被实现为状态机中的模块，其控制存储器阵列中的存储器操作的执行。

9. 发明申请

WO2007131062A3 NON-VOLATILE MEMORY WITH BACKGROUND DATA LATCH CACHING DURING READ OPERATIONS AND METHODS THEREFOR 审中-公开
标题翻译：具有背景数据的非易失性存储器读取操作期间的缓存及其方法
公开(公告)号：WO2007131062A3
公开(公告)日：2008-03-06
申请号：PCT/US2007068069
申请日：2007-05-02
申请人： SANDISK CORP , LI YAN
发明人： LI YAN
IPC分类号： G11C16/26 , G11C7/22 , G11C11/56
CPC分类号： G11C16/26 , G06F12/0893 , G06F2212/2022 , G06F2212/3042 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/22 , G11C11/5628 , G11C11/5642 , G11C2207/107 , G11C2207/2245 , G11C2207/2281
摘要： Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A scheme for caching read data is implemented so that even when the read for a current page on a current wordline must be preceded by a prerequisite read of data on an adjacent wordline, the prerequisite read along with any I/O access is preemptively done in the cycle for reading a previous page so that the current read can be performed while the previously read page is busy with the I/O access.
摘要翻译：来自存储器读或写操作的部分延迟是通过I / O总线将数据输入或从存储器的数据锁存器输出。存在用于通过允许存储器在存储器核心忙于读取操作的情况下在后台执行这些数据高速缓存和传送操作中的一些的方法和电路来改善非易失性存储器件的性能。实现用于缓存读取数据的方案，使得即使在当前字线上的当前页面的读取必须在相邻字线上的数据读取的前提条件之前，先决条件读取与任何I / O访问一起先于用于读取上一页的循环，以便当先前读取的页面忙于I / O访问时可以执行当前读取。

10. 发明申请

WO2008011440A2 COMPENSATING FOR COUPLING DURING PROGRAMMING 审中-公开
标题翻译：编程期间的耦合补偿
公开(公告)号：WO2008011440A2
公开(公告)日：2008-01-24
申请号：PCT/US2007073739
申请日：2007-07-18
申请人： SANDISK CORP , LI YAN
发明人： LI YAN
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3427 , G11C16/344 , G11C29/00 , G11C2211/5621
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。为了补偿该耦合，给定存储器单元的读取或编程过程可以考虑相邻存储器单元的编程状态。为了确定是否需要补偿，可以执行包括感测关于相邻存储器单元的编程状态的信息（例如，在相邻位线或其他位置上）的处理。

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