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81. 发明授权

US08471356B2 Programmable anti-fuse structures with conductive material islands 失效
标题翻译：具有导电材料岛的可编程抗熔丝结构
公开(公告)号：US08471356B2
公开(公告)日：2013-06-25
申请号：US12761780
申请日：2010-04-16
申请人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Kangguo Cheng , Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： G06F17/50 , H01L21/768 , H01L23/525
CPC分类号： H01L23/5252 , G06F17/505 , H01L2924/0002 , H01L2924/00
摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
摘要翻译：提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

82. 发明授权

US08349697B2 Field effect transistor with air gap dielectric 有权
标题翻译：具有气隙电介质的场效应晶体管
公开(公告)号：US08349697B2
公开(公告)日：2013-01-08
申请号：US13537334
申请日：2012-06-29
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/76
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

83. 发明申请

US20120264275A1 FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC 有权
标题翻译：具有气隙介质的场效应晶体管
公开(公告)号：US20120264275A1
公开(公告)日：2012-10-18
申请号：US13537334
申请日：2012-06-29
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/762
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

84. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

85. 发明授权

US08008696B2 Band gap modulated optical sensor 有权
标题翻译：带隙调制光传感器
公开(公告)号：US08008696B2
公开(公告)日：2011-08-30
申请号：US12146575
申请日：2008-06-26
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
IPC分类号： H01L29/72
CPC分类号： H01L27/14645 , H01L27/14627
摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.
摘要翻译：互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素半导体层的材料。电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。此外，还提供了本发明的互补金属氧化物半导体（CMOS）图像传感器的设计结构。

86. 发明申请

US20110095393A1 CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS 有权
标题翻译：创造出具有重大均匀厚度的极细半导体绝缘体（ETSOI）
公开(公告)号：US20110095393A1
公开(公告)日：2011-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06 , H01L21/66 , C23F1/08
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

87. 发明授权

US07790564B2 Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations 失效
标题翻译：使用多深度浅沟槽隔离件在绝缘体上半导体衬底上制造有源器件的方法
公开(公告)号：US07790564B2
公开(公告)日：2010-09-07
申请号：US12108851
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/331 , H01L21/76 , H01L21/22 , H01L21/38 , H01L21/762
CPC分类号： H01L21/7624
摘要： Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.
摘要翻译：在绝缘体上半导体衬底中制造器件结构的方法。该方法包括在衬底器件层中形成第一隔离区，该第一隔离区从器件层的顶表面延伸到第一深度，并且在半导体层中形成第二隔离区，该半导体层从半导体层的顶表面延伸到第二隔离区深度大于第一深度。该方法还包括在垂直位于第一隔离区域和绝缘层之间的半导体层中形成器件结构的掺杂区域。

88. 发明授权

US07776680B2 Complementary metal oxide semiconductor device with an electroplated metal replacement gate 失效
标题翻译：具有电镀金属置换栅的互补金属氧化物半导体器件
公开(公告)号：US07776680B2
公开(公告)日：2010-08-17
申请号：US11968885
申请日：2008-01-03
申请人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
发明人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/517 , H01L29/66545
摘要： Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).
摘要翻译：本文公开了一种形成互补金属氧化物半导体（CMOS）器件的方法的实施例，该器件具有至少一个高纵横比栅极结构，其中无空隙和无缝的金属栅极导体层位于相对薄的高压 k栅介质层。这些方法实施例包括栅极替换策略，其使用电镀工艺从底部向上填充具有金属栅极导体层的高纵横比栅极堆叠开口。用于电镀工艺的电子源是直接通过衬底背面的电流。这消除了对种子层的需要，并且确保金属栅极导体层将形成为没有空隙或接缝。此外，根据实施例，电镀工艺在照明下进行，以增强电子流向给定区域（即，为了增强电镀）或在黑暗中以防止电子流向给定区域（即防止电镀）。

89. 发明授权

US07687883B2 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US07687883B2
公开(公告)日：2010-03-30
申请号：US11627723
申请日：2007-01-26
申请人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
发明人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

90. 发明授权

US07442583B2 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable 有权
标题翻译：使用电可编程保险丝隐藏架构，防止逆向工程，并使设备无法工作
公开(公告)号：US07442583B2
公开(公告)日：2008-10-28
申请号：US11016219
申请日：2004-12-17
申请人： Anthony R. Bonaccio , Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Anthony R. Bonaccio , Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

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