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    • 82. 发明授权
    • System and method for active control of BPSG deposition
    • 用于主动控制BPSG沉积的系统和方法
    • US06828162B1
    • 2004-12-07
    • US09894434
    • 2001-06-28
    • Arvind HalliyalBhanwar SinghMichael K. TempletonRamkumar Subramanian
    • Arvind HalliyalBhanwar SinghMichael K. TempletonRamkumar Subramanian
    • H01L2100
    • H01L21/67253G01N21/4738H01L21/02129H01L21/31625
    • A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof. The processor selectively controls the reflow controlling devices so as to regulate temperature of the respective portions of the wafer.
    • 提供了一种用于监测和控制硼磷掺杂氧化硅(BPSG)沉积和回流工艺的系统。 该系统包括一个或多个光源,每个光源将光引导到沉积BPSG的晶片的一个或多个部分。 从BPSG反射的光被测量系统收集,该系统处理收集的光。 通过BPSG的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的BPSG沉积的一致性。 测量系统将BPSG沉积相关数据提供给确定晶片各部分的BPSG沉积的处理器。 该系统还包括多个回流控制装置,每个这样的装置对应于晶片的相应部分并提供加热和/或冷却。 处理器选择性地控制回流控制装置,以便调节晶片各部分的温度。
    • 85. 发明授权
    • Gate oxide thickness measurement and control using scatterometry
    • 栅极氧化层厚度测量与控制采用散射法
    • US06727995B1
    • 2004-04-27
    • US09903884
    • 2001-07-12
    • Arvind HalliyalBhanwar SinghRamkumar Subramanian
    • Arvind HalliyalBhanwar SinghRamkumar Subramanian
    • G01B1106
    • H01L21/28194G01B11/0625H01L21/67253H01L29/517H01L29/518
    • A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.
    • 提供了一种用于调节栅氧化层形成的系统。 该系统包括一个或多个光源,每个光源将光引导到在晶片上沉积和/或形成的一个或多个栅极氧化物层。 从栅极氧化层反射的光被测量系统收集,该系统处理所收集的光。 所收集的光表示晶片上各个栅极氧化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据,其确定晶片上各个栅极氧化物层的厚度和/或均匀性。 该系统还包括多个栅极氧化物层形成器,其中每个栅极氧化物形成体对应于晶片的相应部分并且在其上形成栅极氧化物层。 处理器选择性地控制栅极氧化物层形成器以调节在晶片上的各个栅极氧化物层形成上的栅极氧化物层形成。
    • 86. 发明授权
    • Oxide/nitride or oxide/nitride/oxide thickness measurement using scatterometry
    • 使用散射测量的氧化物/氮化物或氧化物/氮化物/氧化物厚度测量
    • US06589804B1
    • 2003-07-08
    • US09904089
    • 2001-07-12
    • Arvind HalliyalBhanwar SinghRamkumar Subramanian
    • Arvind HalliyalBhanwar SinghRamkumar Subramanian
    • H01L2100
    • G01B11/0625
    • A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon. The processor selectively controls the oxide/nitride formers to regulate oxide and/or nitride layer formation on the respective ON and/or ONO formations on the wafer.
    • 提供了一种用于调节ON和/或ONO电介质形成的系统。 该系统包括一个或多个光源,每个光源将光引导到在晶片上沉积和/或形成的一个或多个氧化物和/或氮化物层。 从氧化物和/或氮化物层反射的光被测量系统收集,该系统处理收集的光。 所收集的光指示晶片上各个氧化物和/或氮化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据,其确定晶片上相应氧化物和/或氮化物层的厚度和/或均匀性。 该系统还包括多个氧化物/氮化物成形器; 每个氧化物/氮化物成形器对应于晶片的相应部分并且在其上提供ON和/或ONO形成。 处理器选择性地控制氧化物/氮化物成形器以调节晶片上相应的ON和/或ONO形成上的氧化物和/或氮化物层的形成。
    • 87. 发明授权
    • Active control of phase shift mask etching process
    • 主动控制相移掩模蚀刻工艺
    • US06562248B1
    • 2003-05-13
    • US09817518
    • 2001-03-26
    • Ramkumar SubramanianBhanwar SinghMichael K. Templeton
    • Ramkumar SubramanianBhanwar SinghMichael K. Templeton
    • G01N2100
    • G03F1/84G03F1/26
    • A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.
    • 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源,每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集,该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。
    • 88. 发明授权
    • Wafer based temperature sensors for characterizing chemical mechanical polishing processes
    • 用于表征化学机械抛光工艺的基于晶圆的温度传感器
    • US06562185B2
    • 2003-05-13
    • US09955552
    • 2001-09-18
    • Steven C. AvanzinoBhanwar SinghBharath RangarajanRamkumar Subramanian
    • Steven C. AvanzinoBhanwar SinghBharath RangarajanRamkumar Subramanian
    • B24B3700
    • B24B37/015
    • A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.
    • 提供了表征化学机械抛光工艺的系统。 该系统包括具有位于金属,多晶硅和/或电介质层和/或衬底中和/或上的金属,多晶硅和/或电介质层和/或衬底和温度传感器的晶片。 该系统还包括一个温度监控系统,可以从温度传感器读取晶圆温度,并且可以分析晶圆温度以表征化学机械抛光过程。 这种表征包括产生关于晶片温度和抛光速率之间的关系的信息,抛光均匀性和在抛光期间引入缺陷。 这些关系与晶片温度相关,如与抛光时间,压力,速度,浆料性质和晶片/金属层性质等参数相关。 可以采用这种表征,例如,更好地理解CMP工艺,以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备 。
    • 89. 发明授权
    • Using localized ionizer to reduce electrostatic charge from wafer and mask
    • 使用局部电离器来减少晶片和掩模的静电电荷
    • US06507474B1
    • 2003-01-14
    • US09597126
    • 2000-06-19
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBryan K. ChooBharath Rangarajan
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBryan K. ChooBharath Rangarajan
    • H01T2300
    • G03F7/70616G03F7/70941
    • One aspect of the present invention elates to a method of reducing electrostatic charges on a patterned photoresist to improve evaluation of the developed photoresist, involving the steps of evaluating the patterned photoresist to determine if electrostatic charges exist thereon; positioning an ionizer near the patterned photoresist, the ionizer generating ions thereby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam. Another aspect of the present invention relates to a system for reducing electrostatic charges on a patterned photoresist, containing a charge sensor for determining if electrostatic charges exist on the patterned photoresist and measuring the electrostatic charges; an ionizer positioned near the patterned photoresist having electrostatic charges thereon for reducing the electrostatic charges on the patterned photoresist; a controller for setting at least one of time of ion generation and amount of ion generation by the ionizer, the controller coupled to the charge sensor and the ionizer; and a scanning electron microscope or an atomic force microscope for evaluating the patterned photoresist having reduced electrostatic charges thereon with an electron beam.
    • 本发明的一个方面是提供减少图案化光致抗蚀剂上的静电电荷以改进对显影光致抗蚀剂的评估的方法,包括评估图案化光致抗蚀剂以确定静电电荷是否存在于其中的步骤; 在图案化的光致抗蚀剂附近定位电离器,离子发生器产生离子,从而减少图案化光致抗蚀剂上的静电电荷; 并用电子束评估图案化的光致抗蚀剂。 本发明的另一方面涉及一种用于减少图案化光致抗蚀剂上的静电电荷的系统,其包含用于确定图案化光致抗蚀剂上是否存在静电电荷并测量静电电荷的电荷传感器; 位于图案化的光致抗蚀剂附近的电离器,其上具有静电电荷,用于减少图案化光致抗蚀剂上的静电电荷; 用于设置离子发生时间和离子发生量中的至少一个的控制器,耦合到电荷传感器和离子发生器的控制器; 以及扫描电子显微镜或原子力显微镜,用于用电子束评估其上具有降低的静电电荷的图案化光致抗蚀剂。
    • 90. 发明授权
    • Conducting electron beam resist thin film layer for patterning of mask plates
    • 用于掩模板图形化的导电电子束抗蚀剂薄膜层
    • US06482558B1
    • 2002-11-19
    • US09782382
    • 2001-02-12
    • Bhanwar SinghRamkumar SubramanianBharath Rangarajan
    • Bhanwar SinghRamkumar SubramanianBharath Rangarajan
    • G03F900
    • G03F7/093G03F1/40G03F1/50Y10S430/143
    • One aspect of the present invention relates to a system for dissipating electrostatic charge on a mask plate structure containing the mask plate structure containing a substrate, a chromium layer over the substrate, and a conductive polymer over the chromium layer; a conductive structure coupled to the mask plate structure which allows accumulated electrostatic charge to flow from the mask plate structure; a conductive path between the conductive structure and a ground, wherein the conductive path inacludes a switch controlled by a controller; and a detector coupled to the controller for signaling the controller when the accumulation of electrostatic charge is detected. Another aspect of the present invention relates to a method for dissipating charge accumulation during patterning of mask plates using a conductive polymer layer involving the steps of providing a mask substrate having a chromium layer; depositing a conductive polymer layer over the chromium layer; connecting a conductive structure to the mask substrate; irradiating portions of the mask substrate with an electron beam; detecting whether electrostatic charge exists on the mask substrate; and if electrostatic charge is detected, closing a circuit whereby the conductive structure is grounded to permit a flow of electrostatic charge from the mask substrate to the ground.
    • 本发明的一个方面涉及一种用于在掩模板结构上耗散静电电荷的系统,该系统包含含有衬底的掩模板结构,在衬底上的铬层和在铬层上的导电聚合物; 耦合到掩模板结构的导电结构,其允许积聚的静电电荷从掩模板结构流动; 导电结构和地之间的导电路径,其中导电路径不允许由控制器控制的开关; 以及耦合到控制器的检测器,用于在检测到静电电荷的累积时用于发信号通知控制器。 本发明的另一方面涉及一种使用导电聚合物层在掩模板图案化期间耗散电荷累积的方法,包括以下步骤:提供具有铬层的掩模基板; 在所述铬层上沉积导电聚合物层; 将导电结构连接到所述掩模基板; 用电子束照射掩模基板的部分; 检测在掩模基板上是否存在静电电荷; 并且如果检测到静电电荷,则关闭电路,由此导电结构接地以允许静电电荷从掩模基板流到地面。