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81. 发明授权

US07444544B2 Write filter cache method and apparatus for protecting the microprocessor core from soft errors 失效
标题翻译：用于保护微处理器内核免受软错误的写入过滤器高速缓存方法和装置
公开(公告)号：US07444544B2
公开(公告)日：2008-10-28
申请号：US11487196
申请日：2006-07-14
申请人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
发明人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F12/0804 , G06F11/1497 , G06F2212/1032
摘要： A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.
摘要翻译：提供了一种用于保护微处理器内核免受软错误的写过滤器高速缓存系统及其方法。在一个方面，来自处理器核心的要写入主高速缓存存储器（例如，L1高速缓存存储器系统）的数据被缓存在放置在主高速缓冲存储器和处理器核心之间的写入过滤器高速缓存中。只有在验证主线程的数据是软错误的情况下，例如通过将主线程的数据与其冗余线程的数据进行比较，才能将写入过滤器的数据移动到主缓存器。主缓存只保留与接受检查点关联的干净数据。

82. 发明申请

US20080016393A1 Write filter cache method and apparatus for protecting the microprocessor core from soft errors 失效
公开(公告)号：US20080016393A1
公开(公告)日：2008-01-17
申请号：US11487196
申请日：2006-07-14
申请人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
发明人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1497 , G06F2212/1032
摘要： A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.

83. 发明授权

US07921331B2 Write filter cache method and apparatus for protecting the microprocessor core from soft errors 有权
标题翻译：用于保护微处理器内核免受软错误的写入过滤器高速缓存方法和装置
公开(公告)号：US07921331B2
公开(公告)日：2011-04-05
申请号：US12138099
申请日：2008-06-12
申请人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
发明人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
IPC分类号： G06F11/00 , G06F11/08
CPC分类号： G06F12/0804 , G06F11/1497 , G06F2212/1032
摘要： A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.
摘要翻译：提供了一种用于保护微处理器内核免受软错误的写过滤器高速缓存系统及其方法。在一个方面，来自处理器核心的要写入主高速缓存存储器（例如，L1高速缓存存储器系统）的数据被缓存在放置在主高速缓冲存储器和处理器核心之间的写入过滤器高速缓存中。只有在验证主线程的数据是软错误的情况下，例如通过将主线程的数据与其冗余线程的数据进行比较，才能将写入过滤器的数据移动到主缓存器。主缓存只保留与接受检查点关联的干净数据。

84. 发明授权

US07818696B2 Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores 有权
标题翻译：基于建筑级吞吐量的功率建模方法和设备，用于普及时钟门控处理器内核
公开(公告)号：US07818696B2
公开(公告)日：2010-10-19
申请号：US11780712
申请日：2007-07-20
申请人： Pradip Bose , Tejas S. Karkhanis , Srinivasan Ramani , Malcolm Scott Ware , Ken Vu
发明人： Pradip Bose , Tejas S. Karkhanis , Srinivasan Ramani , Malcolm Scott Ware , Ken Vu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
摘要翻译：一种用于估计由处理器核心处理工作负载的功率消耗的方法 - 包括分析参考测试用例以生成参考工作负载特征，分析实际工作负载以产生实际工作负载特性，对参考测试用例执行功率分析以建立参考功耗值，并根据实际和参考工作负载特性和参考功耗值估计实际工作负载功耗值。

85. 发明授权

US07506216B2 System and method of workload-dependent reliability projection and monitoring for microprocessor chips and systems 失效
标题翻译：基于工作负载的可靠性投影和微处理器芯片和系统的监控方法
公开(公告)号：US07506216B2
公开(公告)日：2009-03-17
申请号：US10829741
申请日：2004-04-21
申请人： Pradip Bose , Jude A. Rivers , Jayanth Srinivasan
发明人： Pradip Bose , Jude A. Rivers , Jayanth Srinivasan
IPC分类号： G06F11/00 , G06F11/34
CPC分类号： G06F11/008 , G06F11/3419 , G06F11/348 , G06F2201/88
摘要： A system and method for projecting reliability includes a module, such as a chip, which includes workload inputs, which account for activity on the chip. A reliability module interacts with the chip to determine a reliability measurement for the chip based upon the workload inputs such that functions of the chip are altered based upon the reliability measurement. The reliability measurements are employed to rate or improve chip designs or calculate a reliability measure in real-time.
摘要翻译：用于投影可靠性的系统和方法包括诸如芯片的模块，其包括工作负载输入，其考虑到芯片上的活动。可靠性模块与芯片交互以基于工作负载输入来确定芯片的可靠性测量，使得基于可靠性测量改变芯片的功能。可靠性测量被用于评估或改进芯片设计或实时计算可靠性测量。

86. 发明授权

US07308593B2 Interlocked synchronous pipeline clock gating 有权
标题翻译：联锁同步管道时钟门控
公开(公告)号：US07308593B2
公开(公告)日：2007-12-11
申请号：US11376544
申请日：2006-03-14
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种包括管道的集成电路和操作管道的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

87. 发明授权

US07249331B2 Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores 有权
标题翻译：基于建筑级吞吐量的功率建模方法和设备，用于普及时钟门控处理器内核
公开(公告)号：US07249331B2
公开(公告)日：2007-07-24
申请号：US10960730
申请日：2004-10-07
申请人： Pradip Bose , Tejas S. Karkhanis , Srinivasan Ramani , Malcolm Scott Ware , Ken Vu
发明人： Pradip Bose , Tejas S. Karkhanis , Srinivasan Ramani , Malcolm Scott Ware , Ken Vu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method for estimating power dissipated by processor core processing a workload includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
摘要翻译：用于估计由处理器核心处理工作负载消耗的功率的方法包括分析参考测试用例以生成参考工作负载特性，分析实际工作负载以产生实际工作负载特性，对参考测试用例执行功率分析以建立参考功率消耗值，并根据实际和参考工作负载特性以及参考功耗值估计实际工作负载功耗值。

88. 发明申请

US20060080625A1 Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores 有权
标题翻译：基于建筑级吞吐量的功率建模方法和设备，用于普及时钟门控处理器内核
公开(公告)号：US20060080625A1
公开(公告)日：2006-04-13
申请号：US10960730
申请日：2004-10-07
申请人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
发明人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test case to establish a reference power dissipation value. Estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value
摘要翻译：一种用于估计由处理器核心处理工作负载消耗的功率的方法，系统和装置，其中所述方法包括分析参考测试用例以生成参考工作负载特性。分析实际工作负载以生成实际工作负载特性。对参考测试用例进行功率分析，建立参考功耗值。根据实际和参考工作负载特性以及参考功耗值估算实际工作负载功耗值

89. 发明授权

US08949101B2 Hardware execution driven application level derating calculation for soft error rate analysis 有权
标题翻译：软件错误率分析的硬件执行驱动应用级降额计算
公开(公告)号：US08949101B2
公开(公告)日：2015-02-03
申请号：US13271827
申请日：2011-10-12
申请人： Pradip Bose , Meeta S. Gupta , Prabhakar N. Kudva , Daniel A. Prener
发明人： Pradip Bose , Meeta S. Gupta , Prabhakar N. Kudva , Daniel A. Prener
IPC分类号： G01R31/3181 , G06F17/50 , G01R31/3183
CPC分类号： G01R31/31816 , G01R31/318357 , G06F17/5022
摘要： Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.
摘要翻译：提供了用于预测软错误对集成电路器件设计的影响的机制。数据处理系统被配置为实现统一的降额工具，其包括用于生成机器降额信息的机器降额前端引擎和用于生成应用降额信息的应用降级前端引擎用于集成电路器件设计。机器降额前端引擎执行集成电路设备设计的仿真以生成机器降额信息。应用降级前端引擎在架构上与集成电路设备设计类似的现有硬件上执行应用程序工作负载，并在执行应用程序工作负载期间将故障注入到现有硬件中，以生成应用程序降级信息。机器降额信息与应用降级信息组合以产生用于集成电路设备设计的至少一个软错误率值。

90. 发明授权

US08091050B2 Modeling system-level effects of soft errors 有权
标题翻译：建模软错误的系统级影响
公开(公告)号：US08091050B2
公开(公告)日：2012-01-03
申请号：US12243427
申请日：2008-10-01
申请人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
发明人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.
摘要翻译：提供了对软错误的系统级别影响进行建模的机制。提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档设计。基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

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