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81. 发明授权

US5394121A Wiring topology for transfer of electrical signals 失效
标题翻译：用于传输电信号的接线拓扑
公开(公告)号：US5394121A
公开(公告)日：1995-02-28
申请号：US137529
申请日：1993-10-15
申请人： Thomas M. Cipolla , Paul W. Coteus , William R. Hardell, Jr.
发明人： Thomas M. Cipolla , Paul W. Coteus , William R. Hardell, Jr.
IPC分类号： G11C7/10 , H01P5/12
CPC分类号： G11C7/1048
摘要： Wiring topology and hierarchy of transmission line impedances for connecting I/O of semiconductor devices together. This arrangement gives smooth signal shapes for signal rise and fall times as fast as one (1) nsec or faster. The design uses a balanced multi-way branched net with increasing impedance until very close to the end, of the net, where it is a balanced multi-way branched net with unterminated ends. Thus, coming out of the signal driver is a single impedance transmission line. This single impedance transmission line (A) then branches into two impedance transmission lines (B), each having an impedance higher than the single line impedance that feeds it. These lines (B) are used to drive electronic modules. After entering the electronic modules through a connector, each of these lines (B) then branch into two transmission lines (C) having a yet higher impedance value. Each of these lines (C) finally ends in a cluster of four transmission lines (D. Each of these final lines (D) connects to electronic devices on the electronic module.
摘要翻译：用于将半导体器件的I / O连接在一起的传输线阻抗的布线拓扑和层次结构。这种布置为信号上升和下降时间提供平滑的信号形状，速度可达一（1）nsec或更快。该设计使用一个平衡的多路分支网络，其阻抗增加到非常接近网络的末端，在那里它是一个平衡的多路分支网络，没有终端。因此，从信号驱动器出来的是单阻抗传输线。该单阻抗传输线（A）然后分支成两个阻抗传输线（B），每条阻抗传输线具有高于馈送它的单线路阻抗的阻抗。这些线（B）用于驱动电子模块。在通过连接器进入电子模块之后，这些线（B）中的每一条然后分支成具有更高阻抗值的两条传输线（C）。这些线（C）中的每一条最终终止于四条传输线的群集（D.这些最后一行（D）中的每一行连接到电子模块上的电子设备。

82. 发明授权

US5343366A Packages for stacked integrated circuit chip cubes 失效
标题翻译：堆叠集成电路芯片立方体的封装
公开(公告)号：US5343366A
公开(公告)日：1994-08-30
申请号：US903838
申请日：1992-06-24
申请人： Thomas M. Cipolla , Paul W. Coteus , Ioannis Damianakis , Glen W. Johnson , Peter G. Ledermann , Linda C. Matthew , Lawrence S. Mok
发明人： Thomas M. Cipolla , Paul W. Coteus , Ioannis Damianakis , Glen W. Johnson , Peter G. Ledermann , Linda C. Matthew , Lawrence S. Mok
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07 , H05K1/14 , H05K1/18 , H05K3/32 , H05K3/34 , H05K3/36 , H05K3/40 , H01R23/68
CPC分类号： H05K3/363 , H01L24/01 , H01L25/0652 , H01L25/0657 , H01L2225/06551 , H01L2225/06596 , H01L2924/09701 , H01L2924/14 , H01L2924/3011 , H05K2201/0397 , H05K2201/048 , H05K2201/09172 , H05K2201/09909 , H05K2201/10484 , H05K2201/1059 , H05K2201/10681 , H05K2201/10984 , H05K3/326 , H05K3/3452 , H05K3/3457 , H05K3/366 , H05K3/4007 , H05K3/4092
摘要： This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.
摘要翻译：本发明涉及将集成电路芯片三维封装成堆栈以形成立方体结构。在堆叠中的相邻芯片之间，设置有电互连装置，其是具有多个导体的第一基板，其多个导体电连接到芯片接触位置，并且其另一端延伸到芯片堆叠的一侧，形成多个针状电互连组件。销状结构可以由在其至少一侧上具有电导体的第一基板的凸起从该侧延伸形成。或者，销状结构可以由从第一基板的边缘的两侧悬臂的导体形成，并且其中来自两侧的相应导体对准并且间隔开第一基板厚度。这些空间包含焊料并形成焊料加载的针状结构。销状结构可以直接焊接到第二衬底表面上的导体上，或者针状结构可以适于插入到第二衬底中的孔中。第二基板提供用于电连接多个这些长方体的装置。优选地，第一和第二基底是电路化柔性聚合物膜。第二基板设置在诸如PC板的第三基板上，其间具有弹性材料，其允许将散热器压紧成与长方体结构的相对侧紧密接触。

83. 发明授权

US5337218A Circuit card interconnecting structure 失效
标题翻译：电路卡互连结构
公开(公告)号：US5337218A
公开(公告)日：1994-08-09
申请号：US892075
申请日：1992-06-02
申请人： Thomas M. Cipolla , Paul W. Coteus
发明人： Thomas M. Cipolla , Paul W. Coteus
IPC分类号： H01R12/50 , H01R12/52 , H01R12/88 , H05K1/14 , H05K3/36 , H05K7/14 , H01R23/68
CPC分类号： H01R12/52 , H01R23/68 , H05K1/14 , H05K1/148 , H05K7/1404 , H01R12/88 , Y10T29/49201
摘要： An interconnecting structure in which circuit and componentry bearing cards are retained in contact with an intermediate card that has component and circuitry areas, and socket insertion contacts.
摘要翻译：一种互连结构，其中电路和元件轴承卡与具有部件和电路区域的中间卡以及插座插入触点保持接触。

84. 发明授权

US5113565A Apparatus and method for inspection and alignment of semiconductor chips and conductive lead frames 失效
标题翻译：半导体芯片和导电引线框架的检查和对准的装置和方法
公开(公告)号：US5113565A
公开(公告)日：1992-05-19
申请号：US549577
申请日：1990-07-06
申请人： Thomas M. Cipolla , Paul W. Coteus , Glen W. Johnson , Philip Murphy , Christopher W. Oden
发明人： Thomas M. Cipolla , Paul W. Coteus , Glen W. Johnson , Philip Murphy , Christopher W. Oden
IPC分类号： H01L21/60 , H01L21/00 , H01L21/66 , H01L21/68
CPC分类号： H01L21/67144 , H01L22/12 , H01L2924/0002 , Y10T29/41 , Y10T29/49121 , Y10T29/49131 , Y10T29/49133 , Y10T29/53178
摘要： A method is described for aligning a contact pattern on an electronic device held by a first movable support, with a bond site pattern on a lead frame held by a second movable support. The method includes the steps of: (a) creating and storing models of a chip's contact pattern and a lead frame's bond site pattern; (b) imaging the electronic device and lead frame; (c) determining the position of contacts on said electronic device and reorienting the contact pattern model to a best fit with the imaged contact position; (d) determining the position of each bond site on the imaged lead frame and reorienting the bond site model to a best fit with the imaged bond site position; (e) determining positional differences between the reoriented lead frame and contact pattern models; and (f) generating signals to reorient the first and second movable supports to minimize the positional differences when they are moved into a bonding positon. A machine is described for performing the above method wherein each of three main movable elements of the machine is assigned a dimensional axis in which its travel is non-adjustable, so that other movable elements can be calibrated thereagainst.

85. 发明授权

US09077616B2 T-star interconnection network topology 有权
标题翻译： T星互连网络拓扑
公开(公告)号：US09077616B2
公开(公告)日：2015-07-07
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/24 , H04L12/715
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

86. 发明申请

US20140071778A1 MEMORY DEVICE REFRESH 有权
标题翻译：存储设备刷新
公开(公告)号：US20140071778A1
公开(公告)日：2014-03-13
申请号：US13609655
申请日：2012-09-11
申请人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
发明人： Paul W. Coteus , Douglas J. Joseph , Kyu-hyoun Kim
IPC分类号： G11C11/402
CPC分类号： G11C11/40611 , G06F13/1668 , Y02D10/14
摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.
摘要翻译：根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。基于接收到同步命令，内存刷新定时器在存储器设备内复位。基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

87. 发明申请

US20140044006A1 T-STAR INTERCONNECTION NETWORK TOPOLOGY 有权
标题翻译： T-STAR互联网络拓扑
公开(公告)号：US20140044006A1
公开(公告)日：2014-02-13
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/28
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

88. 发明授权

US08571847B2 Efficiency of static core turn-off in a system-on-a-chip with variation 失效
标题翻译：在具有变化的片上系统中静态磁芯关断的效率
公开(公告)号：US08571847B2
公开(公告)日：2013-10-29
申请号：US12727984
申请日：2010-03-19
申请人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
发明人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
IPC分类号： G06G7/75
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/3237 , G06F11/24 , Y02D10/128 , Y02D10/16
摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.
摘要翻译：一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

89. 发明授权

US08521990B2 Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders 有权
标题翻译：在环网中嵌入全局屏障和集体，每个节点根据类映射将接收器的输入组合到输出到发送器
公开(公告)号：US08521990B2
公开(公告)日：2013-08-27
申请号：US12723277
申请日：2010-03-12
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
IPC分类号： G06F15/16
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
摘要翻译：本发明的实施例提供了一种用于在被组织为环面网络的并行计算机系统中嵌入全局屏障和全局中断网络的方法，系统和计算机程序产品。计算机系统包括多个节点。在一个实施例中，该方法包括从节点的一组接收器中获取输入，将来自接收器的输入划分为多个类，组合每个类的输入以获得结果，并将所述结果发送到一组的节点的发送者。本发明的实施例提供了一种用于将集体网络嵌入组织为环面网络的并行计算机系统中的方法，系统和计算机程序产品。在一个实施例中，该方法包括向环形网络添加集中逻辑以在树结构中的至少一组节点之间路由消息。

90. 发明授权

US08516409B2 Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device 有权
标题翻译：实现垂直管芯堆叠，在多晶硅通孔堆叠半导体器件中分配多个管芯的逻辑功能
公开(公告)号：US08516409B2
公开(公告)日：2013-08-20
申请号：US12944020
申请日：2010-11-11
申请人： Paul W. Coteus , Kyu-Hyoun Kim , Robert B. Tremaine
发明人： Paul W. Coteus , Kyu-Hyoun Kim , Robert B. Tremaine
IPC分类号： G06F17/50
CPC分类号： H01L25/0657 , G11C5/04 , G11C17/143 , G11C17/16 , G11C29/12 , G11C29/785 , G11C29/802 , G11C2229/763 , G11C2229/766 , H01L23/481 , H01L25/18 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565
摘要： A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.
摘要翻译：一种用于实现芯片堆叠以在多个裸片上分布逻辑功能的方法和电路，以及提供了通过硅片通过堆叠的半导体器件的裸片识别和备用，以及设置有被摄体电路的设计结构。管芯堆叠中的每个管芯包括用于实现相应的预定义功能的预定义功能逻辑。在每个相应的管芯中执行相应的预定义功能，并且将相应的功能结果提供给管芯堆叠中的相邻管芯。管芯堆叠中的每个管芯包括用于提供管芯识别的逻辑。通过组合每个管芯上的多个选择的信号来形成操作管芯签名。使用TSV互连将芯片签名耦合到下一级相邻裸片，其中它与该芯片签名组合。

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