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81. 发明申请

US20060094205A1 Method of forming isolation trench with spacer formation 有权
公开(公告)号：US20060094205A1
公开(公告)日：2006-05-04
申请号：US10976869
申请日：2004-11-01
申请人： Srikanteswara Dakshina-Murthy , Douglas Bonser , Mark Kelling , Asuka Nomura
发明人： Srikanteswara Dakshina-Murthy , Douglas Bonser , Mark Kelling , Asuka Nomura
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.

82. 发明授权

US07022596B2 Method for forming rectangular-shaped spacers for semiconductor devices 有权
标题翻译：用于形成用于半导体器件的矩形间隔件的方法
公开(公告)号：US07022596B2
公开(公告)日：2006-04-04
申请号：US10747680
申请日：2003-12-30
申请人： Huicai Zhong , Srikanteswara Dakshina-Murthy
发明人： Huicai Zhong , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/3205
CPC分类号： H01L29/6659 , H01L21/266 , H01L29/6656
摘要： A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.
摘要翻译：半导体器件及其制造方法通过在衬底和栅电极上沉积间隔层形成间隔物并在间隔层上形成保护层。干蚀刻保护层以在间隔层上留下薄膜侧壁。然后蚀刻间隔层，其中保护层保护间隔层的外侧壁。该蚀刻在栅极上产生具有平行于栅电极侧壁延伸的基本垂直侧壁的间隔物。间隔物的I形形状在源/漏离子注入过程中防止穿通，从而提供改进的源极/漏极注入剂量分布。

83. 发明授权

US06979651B1 Method for forming alignment features and back-side contacts with fewer lithography and etch steps 有权
标题翻译：用较少光刻和蚀刻步骤形成对准特征和背面接触的方法
公开(公告)号：US06979651B1
公开(公告)日：2005-12-27
申请号：US10207653
申请日：2002-07-29
申请人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
发明人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/308 , H01L21/311 , H01L21/762 , H01L23/544
CPC分类号： H01L21/76264 , H01L21/3081 , H01L21/31144 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a dielectric material to form the isolation. A second lithography and etch step is then applied to etch the window locations for back-side contacts, and to transfer the alignment marks down into the SOI lower substrate. After this first lithography and etch step, the alignment marks in the top silicon may be used for alignment of the second lithography mask and etch. This is made possible by leaving the polish stop layer on the wafer, which serves to increase the optically effective thickness of the alignment mark pattern. The polish stop layer is removed after the second etch process. The teachings can be applied to any Semiconductor-On-Insulator-type wafer/technology where the top semiconductor layer is not thicker than the optimum alignment mark depth.
摘要翻译：该方法执行第一次光刻和蚀刻，以将浅沟槽隔离特征和对准标记特征形成到顶部SOI层中。然后用介电材料填充浅沟槽以形成隔离。然后施加第二光刻和蚀刻步骤以蚀刻用于背面接触的窗口位置，并将对准标记向下转移到SOI下基板中。在该第一光刻和蚀刻步骤之后，顶部硅中的对准标记可用于对准第二光刻掩模和蚀刻。这可以通过将抛光停止层留在晶片上来实现，其用于增加对准标记图案的光学有效厚度。在第二次蚀刻工艺之后去除抛光停止层。该教导可以应用于任何半导体绝缘体型晶片/技术，其中顶部半导体层不比最佳对准标记深度厚。

84. 发明授权

US06897527B2 Strained channel FinFET 有权
标题翻译：应变通道FinFET
公开(公告)号：US06897527B2
公开(公告)日：2005-05-24
申请号：US10833112
申请日：2004-04-28
申请人： Srikanteswara Dakshina-Murthy , Judy Xilin An , Zoran Krivokapic , Haihong Wang , Bin Yu
发明人： Srikanteswara Dakshina-Murthy , Judy Xilin An , Zoran Krivokapic , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/49 , H01L29/786 , H01L27/01
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/4908 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.
摘要翻译：半导体器件包括翅片和形成在鳍片的至少一部分上的层。翅片包括第一结晶材料。该层包括第二结晶材料，其中第一结晶材料具有比第二结晶材料更大的晶格常数以在层内引起拉伸应变。

85. 发明授权

US06849530B2 Method for semiconductor gate line dimension reduction 失效
公开(公告)号：US06849530B2
公开(公告)日：2005-02-01
申请号：US10334337
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/28 , H01L21/4763
CPC分类号： H01L21/28123
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

86. 发明授权

US06773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning 有权
标题翻译：改进的薄膜堆叠和图案化策略，用于应力补偿和防止无定形碳栅图案中的图案变形
公开(公告)号：US06773998B1
公开(公告)日：2004-08-10
申请号：US10445129
申请日：2003-05-20
申请人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
发明人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
摘要翻译：集成电路的方法包括使用无定形碳ARC掩模。一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

87. 发明授权

US06762483B1 Narrow fin FinFET 有权
标题翻译：窄鳍FinFET
公开(公告)号：US06762483B1
公开(公告)日：2004-07-13
申请号：US10348910
申请日：2003-01-23
申请人： Zoran Krivokapic , Judy Xilin An , Srikanteswara Dakshina-Murthy , Haihong Wang , Bin Yu
发明人： Zoran Krivokapic , Judy Xilin An , Srikanteswara Dakshina-Murthy , Haihong Wang , Bin Yu
IPC分类号： H01L2906
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66818 , H01L29/78687
摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
摘要翻译：一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。该方法还包括使双翅片变薄以产生窄的双翅片。

88. 发明授权

US06696334B1 Method for formation of a differential offset spacer 有权
标题翻译：形成差动偏移间隔物的方法
公开(公告)号：US06696334B1
公开(公告)日：2004-02-24
申请号：US10260485
申请日：2002-09-30
申请人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
发明人： Kay Hellig , Srikanteswara Dakshina-Murthy , Christoph Schwan
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.
摘要翻译：提出了一种适用于掺入高级CMOS技术设备的制造工艺中的差分偏移间隔物形成方法。该方法包括形成覆盖多个栅极结构的第一绝缘层，然后形成覆盖第一绝缘层的第二绝缘层。形成掩模以暴露覆盖第一晶体管类型的栅极结构的第二绝缘层的第一部分，并且保护覆盖第二晶体管类型的晶体管的栅极结构的第二绝缘层的第二部分。然后蚀刻覆盖第一类型的栅极结构的第二绝缘层的暴露的第一部分。在蚀刻之后，去除掩模，并且蚀刻第二绝缘层和第一绝缘层的暴露的第二部分以形成邻接栅极结构的差分间隔物。端点用于停止间隔物蚀刻工艺。

89. 发明授权

US06645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer 有权
标题翻译：在使用牺牲碳层的FinFET器件中形成翅片的方法
公开(公告)号：US06645797B1
公开(公告)日：2003-11-11
申请号：US10310926
申请日：2002-12-06
申请人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.
摘要翻译：一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模。该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

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