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81. 发明授权

US06874137B1 Design data processing method and recording medium 有权
标题翻译：设计数据处理方法和记录介质
公开(公告)号：US06874137B1
公开(公告)日：2005-03-29
申请号：US09708572
申请日：2000-11-09
申请人： Noriyuki Ito , Yoichiro Ishikawa , Hiroaki Hanamitsu , Ryoichi Yamashita
发明人： Noriyuki Ito , Yoichiro Ishikawa , Hiroaki Hanamitsu , Ryoichi Yamashita
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5068
摘要： A design data processing method is a method of processing hierarchically configured design data, comprises the steps of: a) obtaining first design data of a predetermined rank of hierarchy; b) obtaining second design data of a rank of hierarchy higher than the predetermined rank of hierarchy; and c) combining the second design data to the first design data.
摘要翻译：设计数据处理方法是一种处理分级配置的设计数据的方法，包括以下步骤：a）获得预定等级等级的第一设计数据; b）获得高于层级的预定等级的层次级的第二设计数据; 以及c）将所述第二设计数据与所述第一设计数据组合。

82. 发明授权

US06684374B2 Timing budget designing method 有权
标题翻译：时间预算设计方法
公开(公告)号：US06684374B2
公开(公告)日：2004-01-27
申请号：US09984782
申请日：2001-10-31
申请人： Noriyuki Ito , Ryoichi Yamashita , Yoichiro Ishikawa
发明人： Noriyuki Ito , Ryoichi Yamashita , Yoichiro Ishikawa
IPC分类号： G06F1750
CPC分类号： G06F17/5031 , G06F17/5045
摘要： When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.
摘要翻译：当逻辑块构建在LSI逻辑设计阶段时，基于设计者的估计或者在生成网表之后的网表的信息来设置块的引脚之间的最大延迟值。引脚可以分组。引脚之间的连接中的延迟值由最大值表示。此外，逻辑块内的多个内部存储器元件由一个或多个内部锁存器表示。另外，作为引脚和内部锁存器之间或内部锁存器与引脚之间的延迟值，从多个延迟值中选择最大值，并将其设置为代表值。

83. 发明授权

US06678941B1 Method for manufacturing a thin film magnetic head 失效
标题翻译：薄膜磁头制造方法
公开(公告)号：US06678941B1
公开(公告)日：2004-01-20
申请号：US09603970
申请日：2000-06-26
申请人： Koichi Terunuma , Tetsuya Mino , Katsuya Kanakubo , Noriyuki Ito
发明人： Koichi Terunuma , Tetsuya Mino , Katsuya Kanakubo , Noriyuki Ito
IPC分类号： G11B5127
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/3116 , G11B5/313 , G11B5/3153 , G11B5/3163 , G11B5/3909 , G11B5/3967 , G11B2005/3996 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49052
摘要： The invention is a method of manufacturing thin film magnetic heads usable for magnetic recording and reproducing drive devices such as magnetic disk drive devices. The method is characterized by forming a first magnetic film in a primary pattern which is larger than its definitive pattern and of which its edges are located within frames which are used in a frame-plating method for a second magnetic film. The second magnetic film is then formed by the frame-plating method and the first magnetic film is etched into its definitive pattern by using the second magnetic film as a mask.
摘要翻译：本发明是制造可用于磁记录和再现诸如磁盘驱动装置的驱动装置的薄膜磁头的方法。该方法的特征在于形成主要图案中的第一磁性膜，其大于其确定性图案，并且其边缘位于用于第二磁性膜的框架镀覆方法中的框架内。然后通过框架电镀法形成第二磁性膜，并且通过使用第二磁性膜作为掩模将第一磁性膜蚀刻成其确定的图案。

84. 发明授权

US06364964B1 Manufacturing method of spin valve magnetoresistive effect element and manufacturing method of thin-film magnetic head with the element 有权
标题翻译：自旋阀磁阻效应元件的制造方法和薄膜磁头与元件的制造方法
公开(公告)号：US06364964B1
公开(公告)日：2002-04-02
申请号：US09655404
申请日：2000-09-05
申请人： Tetsuro Sasaki , Noriyuki Ito , Koichi Terunuma
发明人： Tetsuro Sasaki , Noriyuki Ito , Koichi Terunuma
IPC分类号： H01F1032
CPC分类号： B82Y25/00 , B82Y10/00 , B82Y40/00 , G11B5/3163 , G11B5/3903 , H01F10/324 , H01F10/3268 , H01F41/302 , H01L43/12 , Y10T29/49034
摘要： The SVMR element has a non-magnetic metallic thin-film layer, first and second ferromagnetic thin-film layers (free and pinned layers) formed to sandwich the non-magnetic metallic thin-film layer and an anti-ferromagnetic thin-film layer formed in contact with a surface of the second ferromagnetic thin-film layer. This surface is opposite to the non-magnetic metallic thin-film layer. The first ferromagnetic thin-film layer has a two-layers structure of a NiFe layer and a CoFe layer. The manufacturing method includes a step of depositing the first ferromagnetic thin-film layer, the non-magnetic metallic thin-film layer, the second ferromagnetic thin-film layer and the anti-ferromagnetic thin-film layer, and a step of annealing, thereafter, the deposited layers so that change in magnetostriction depending upon variation of a thickness of the NiFe layer becomes small.
摘要翻译： SVMR元件具有非磁性金属薄膜层，形成为夹着非磁性金属薄膜层的第一和第二铁磁薄膜层（自由和被钉扎层）和形成的反铁磁性薄膜层与第二铁磁性薄膜层的表面接触。该表面与非磁性金属薄膜层相反。第一铁磁性薄膜层具有NiFe层和CoFe层的两层结构。该制造方法包括沉积第一铁磁薄膜层，非磁性金属薄膜层，第二铁磁性薄膜层和反铁磁性薄膜层的步骤以及退火步骤沉积层，使得依赖于NiFe层的厚度变化的磁致伸缩变化变小。

85. 发明授权

US06240541B1 Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit 有权
标题翻译：交互式电路设计装置，其从布局设计单元显示组件放置和线路布线的结果
公开(公告)号：US06240541B1
公开(公告)日：2001-05-29
申请号：US09227967
申请日：1999-01-11
申请人： Mitsuru Yasuda , Hiroyuki Sugiyama , Noriyuki Ito , Ryoichi Yamashita , Tadashi Konno , Yasunori Abe , Naomi Bizen , Terunobu Maruyama , Yoshiyuki Kato , Tomoyuki Isomura , Hiroshi Ikeda , Miki Takagi
发明人： Mitsuru Yasuda , Hiroyuki Sugiyama , Noriyuki Ito , Ryoichi Yamashita , Tadashi Konno , Yasunori Abe , Naomi Bizen , Terunobu Maruyama , Yoshiyuki Kato , Tomoyuki Isomura , Hiroshi Ikeda , Miki Takagi
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
摘要翻译：一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

86. 发明授权

US5787268A Interactive circuit designing apparatus 失效
标题翻译：交互式电路设计装置
公开(公告)号：US5787268A
公开(公告)日：1998-07-28
申请号：US497375
申请日：1995-06-30
申请人： Yaroku Sugiyama , Hiroyuki Sugiyama , Noriyuki Ito , Ryouichi Yamashita , Terunobu Maruyama , Yasunori Abe
发明人： Yaroku Sugiyama , Hiroyuki Sugiyama , Noriyuki Ito , Ryouichi Yamashita , Terunobu Maruyama , Yasunori Abe
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5022 , G06F17/5045
摘要： The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.
摘要翻译：本发明提供了一种交互式电路设计装置，其中逻辑设计，布局设计和速度分析可以在处理中相互配合。交互式电路设计装置包括用于逻辑设计设计对象电路的逻辑设计部分，布局设计部分，用于基于逻辑设计的结果执行构成设计对象电路的逻辑部件的安装布置，并且在逻辑部件之间执行布线，以及速度分析部件，用于根据布局的结果，基于对设计对象电路中的每个路径的延迟的计算来执行速度分析。逻辑设计部分，布局设计部分和速度分析部分彼此连接，以便在必要时相互配合。交互式电路设计装置适用于设计LSI，印刷电路板等元件的电路的装置。

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