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1. 发明授权

US06874137B1 Design data processing method and recording medium 有权
标题翻译：设计数据处理方法和记录介质
公开(公告)号：US06874137B1
公开(公告)日：2005-03-29
申请号：US09708572
申请日：2000-11-09
申请人： Noriyuki Ito , Yoichiro Ishikawa , Hiroaki Hanamitsu , Ryoichi Yamashita
发明人： Noriyuki Ito , Yoichiro Ishikawa , Hiroaki Hanamitsu , Ryoichi Yamashita
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5068
摘要： A design data processing method is a method of processing hierarchically configured design data, comprises the steps of: a) obtaining first design data of a predetermined rank of hierarchy; b) obtaining second design data of a rank of hierarchy higher than the predetermined rank of hierarchy; and c) combining the second design data to the first design data.
摘要翻译：设计数据处理方法是一种处理分级配置的设计数据的方法，包括以下步骤：a）获得预定等级等级的第一设计数据; b）获得高于层级的预定等级的层次级的第二设计数据; 以及c）将所述第二设计数据与所述第一设计数据组合。

2. 发明授权

US06684374B2 Timing budget designing method 有权
标题翻译：时间预算设计方法
公开(公告)号：US06684374B2
公开(公告)日：2004-01-27
申请号：US09984782
申请日：2001-10-31
申请人： Noriyuki Ito , Ryoichi Yamashita , Yoichiro Ishikawa
发明人： Noriyuki Ito , Ryoichi Yamashita , Yoichiro Ishikawa
IPC分类号： G06F1750
CPC分类号： G06F17/5031 , G06F17/5045
摘要： When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.
摘要翻译：当逻辑块构建在LSI逻辑设计阶段时，基于设计者的估计或者在生成网表之后的网表的信息来设置块的引脚之间的最大延迟值。引脚可以分组。引脚之间的连接中的延迟值由最大值表示。此外，逻辑块内的多个内部存储器元件由一个或多个内部锁存器表示。另外，作为引脚和内部锁存器之间或内部锁存器与引脚之间的延迟值，从多个延迟值中选择最大值，并将其设置为代表值。

3. 发明授权

US07240317B2 Placement/net wiring processing system 有权
标题翻译：放置/网络布线处理系统
公开(公告)号：US07240317B2
公开(公告)日：2007-07-03
申请号：US10625554
申请日：2003-07-24
申请人： Noriyuki Ito , Ryoichi Yamashita , Keiko Osawa , Tomoyuki Isomura , Hiroaki Hanamitsu , Hideaki Katagiri
发明人： Noriyuki Ito , Ryoichi Yamashita , Keiko Osawa , Tomoyuki Isomura , Hiroaki Hanamitsu , Hideaki Katagiri
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associates with placements and wiring which are read out of a storage division and designated by user to the placement and wiring graphic information for display on a screen.
摘要翻译：放置/网络布线处理系统使用交互式编辑器，其简化和简化了放置或移动单元格以及添加，删除或修改布线的操作。布置/网络布线处理系统包括用于控制布局和布线操作和处理程序的执行的控制装置，用于在屏幕上显示布局和布线信息的显示装置，用于操作布局和布线的操作和处理装置屏幕以及用于管理放置和布线信息的信息管理装置。控制装置复制由此读出的程序，然后执行程序。显示装置根据选择在屏幕上显示放置内容和布线图形信息，并且将处理相关信息与从存储部读出并由用户指定的放置和布线图形的布局和布线相关联信息显示在屏幕上。

4. 发明授权

US06629305B2 Placement/net wiring processing system 有权
标题翻译：放置/网络布线处理系统
公开(公告)号：US06629305B2
公开(公告)日：2003-09-30
申请号：US09811772
申请日：2001-03-20
申请人： Noriyuki Ito , Ryoichi Yamashita , Keiko Osawa , Tomoyuki Isomura , Hiroaki Hanamitsu , Hideaki Katagiri
发明人： Noriyuki Ito , Ryoichi Yamashita , Keiko Osawa , Tomoyuki Isomura , Hiroaki Hanamitsu , Hideaki Katagiri
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out Thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associated with placements and wiring which are read out of a storage division and designated by the user to the placement and wiring graphic information for display on the screen.
摘要翻译：放置/网络布线处理系统使用交互式编辑器，其简化和简化了放置或移动单元格以及添加，删除或修改布线的操作。布置/网络布线处理系统包括用于控制布局和布线操作和处理程序的执行的控制装置，用于在屏幕上显示布局和布线信息的显示装置，用于操作布局和布线的操作和处理装置屏幕以及用于管理放置和布线信息的信息管理装置。控制装置复制由此读出的程序，然后执行程序。显示装置根据选择在屏幕上显示放置内容和布线图形信息，并将与由存储部读出并由用户指定的布置和布线相关联的处理相关信息与放置和布线相关联用于在屏幕上显示的图形信息。

5. 发明授权

US07328422B2 Design support apparatus, design support program and design support method for supporting design of semiconductor integrated circuit 有权
标题翻译：设计支持设备，设计支持方案和支持半导体集成电路设计支持方法
公开(公告)号：US07328422B2
公开(公告)日：2008-02-05
申请号：US11059556
申请日：2005-02-17
申请人： Noriyuki Ito , Ryoichi Yamashita
发明人： Noriyuki Ito , Ryoichi Yamashita
IPC分类号： G07F17/50
CPC分类号： G06F17/5072
摘要： A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output terminal of the first cell to be called ‘receiver(s)’, whether or not said driver exists outside a predetermined region for enclosing said receiver(s), and a layout section which determines a base point from an inside of said predetermined region, with respect to said net where it is judged that said driver exists outside said predetermined region, and arranges said diagonal wiring for wiring which connects said output terminal of said driver with said base point when said base point can be connected with an input terminal of said receiver by means of vertical and/or horizontal wiring.
摘要翻译：提供了一种设计支持装置，包括控制部分执行布局程序，以执行位置判断部分，该位置判断部分对每个网络进行位置判断，以检查由被称为“驾驶员”的第一个单元形成的网络，以及一个或多个经由第一单元的输出端被驱动以被称为“接收器”的单元，无论所述驱动器是否存在于用于封闭所述接收器的预定区域之外，以及布局部分，其从内部确定基点所述预定区域相对于所述网络，其中判断为所述驱动器存在于所述预定区域之外，并且当所述基点可以与所述基点连接时，布置所述驱动器的所述输出端子与所述基点连接的布线的所述对角线布线所述接收器的输入端通过垂直和/或水平布线。

6. 发明授权

US5889677A Circuit designing apparatus of an interactive type 失效
标题翻译：交互式电路设计装置
公开(公告)号：US5889677A
公开(公告)日：1999-03-30
申请号：US574901
申请日：1995-12-19
申请人： Mitsuru Yasuda , Hiroyuki Sugiyama , Noriyuki Ito , Ryoichi Yamashita , Tadashi Konno , Yasunori Abe , Naomi Bizen , Terunobu Maruyama , Yoshiyuki Kato , Tomoyuki Isomura , Hiroshi Ikeda , Miki Takagi
发明人： Mitsuru Yasuda , Hiroyuki Sugiyama , Noriyuki Ito , Ryoichi Yamashita , Tadashi Konno , Yasunori Abe , Naomi Bizen , Terunobu Maruyama , Yoshiyuki Kato , Tomoyuki Isomura , Hiroshi Ikeda , Miki Takagi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
摘要翻译：一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有速度分析单元，用于对要设计的电路上的每个布线路径执行延迟计算，以及显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

7. 发明授权

US07240318B2 Placement/net wiring processing system 有权
公开(公告)号：US07240318B2
公开(公告)日：2007-07-03
申请号：US10625631
申请日：2003-07-24
申请人： Noriyuki Ito , Ryoichi Yamashita , Keiko Osawa , Tomoyuki Isomura , Hiroaki Hanamitsu , Hideaki Katagiri
发明人： Noriyuki Ito , Ryoichi Yamashita , Keiko Osawa , Tomoyuki Isomura , Hiroaki Hanamitsu , Hideaki Katagiri
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associates with placements and wiring which are read out of a storage division and designated by user to the placement and wiring graphic information for display on a screen.

8. 发明申请

US20060112365A1 Design support apparatus, design support program and design support method for supporting design of semiconductor integrated circuit 有权
标题翻译：设计支持设备，设计支持方案和支持半导体集成电路设计支持方法
公开(公告)号：US20060112365A1
公开(公告)日：2006-05-25
申请号：US11059556
申请日：2005-02-17
申请人： Noriyuki Ito , Ryoichi Yamashita
发明人： Noriyuki Ito , Ryoichi Yamashita
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072
摘要： A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output terminal of the first cell to be called ‘receiver(s)’, whether or not said driver exists outside a predetermined region for enclosing said receiver(s), and a layout section which determines a base point from an inside of said predetermined region, with respect to said net where it is judged that said driver exists outside said predetermined region, and arranges said diagonal wiring for wiring which connects said output terminal of said driver with said base point when said base point can be connected with an input terminal of said receiver by means of vertical and/or horizontal wiring.
摘要翻译：提供了一种设计支持装置，包括控制部分执行布局程序，以执行位置判断部分，该位置判断部分对每个网络进行位置判断，以检查由被称为“驾驶员”的第一个单元形成的网络，以及一个或多个经由第一单元的输出端被驱动以被称为“接收器”的单元，无论所述驱动器是否存在于用于封闭所述接收器的预定区域之外，以及布局部分，其从内部确定基点所述预定区域相对于所述网络，其中判断为所述驱动器存在于所述预定区域之外，并且当所述基点可以与所述基点连接时，布置所述驱动器的所述输出端子与所述基点连接的布线的所述对角线布线所述接收器的输入端通过垂直和/或水平布线。

9. 发明授权

US06240541B1 Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit 有权
标题翻译：交互式电路设计装置，其从布局设计单元显示组件放置和线路布线的结果
公开(公告)号：US06240541B1
公开(公告)日：2001-05-29
申请号：US09227967
申请日：1999-01-11
申请人： Mitsuru Yasuda , Hiroyuki Sugiyama , Noriyuki Ito , Ryoichi Yamashita , Tadashi Konno , Yasunori Abe , Naomi Bizen , Terunobu Maruyama , Yoshiyuki Kato , Tomoyuki Isomura , Hiroshi Ikeda , Miki Takagi
发明人： Mitsuru Yasuda , Hiroyuki Sugiyama , Noriyuki Ito , Ryoichi Yamashita , Tadashi Konno , Yasunori Abe , Naomi Bizen , Terunobu Maruyama , Yoshiyuki Kato , Tomoyuki Isomura , Hiroshi Ikeda , Miki Takagi
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
摘要翻译：一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

10. 发明授权

US08171444B2 Layout design method, apparatus and storage medium 有权
标题翻译：布局设计方法，设备和存储介质
公开(公告)号：US08171444B2
公开(公告)日：2012-05-01
申请号：US12561583
申请日：2009-09-17
申请人： Ryoichi Yamashita
发明人： Ryoichi Yamashita
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a layout for determining the disposition of each cell in the second module and wiring for each second module.
摘要翻译：布局设计支持装置将通过将半导体集成电路分割成多个第二模块而获得的第一模块分割为支持用于确定构成半导体集成电路和布线的每个单元的布置的布局设计，并且使详细设计用于确定第二模块中的每个单元的布置以及用于每个第二模块的布线的布局。

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