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81. 发明申请

US20100008153A1 METHOD FOR OPERATING NONVOLATITLE MEMORY ARRAY 有权
标题翻译：操作非易失性存储器阵列的方法
公开(公告)号：US20100008153A1
公开(公告)日：2010-01-14
申请号：US12561849
申请日：2009-09-17
申请人： Hao-Ming Lien , Ming-Hsiu Lee
发明人： Hao-Ming Lien , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.
摘要翻译：一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

82. 发明授权

US07608886B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US07608886B2
公开(公告)日：2009-10-27
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个电池的位数，并实现更高密度的存储器阵列。

83. 发明申请

US20080266932A1 CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT 有权
标题翻译：编程记忆元件电路
公开(公告)号：US20080266932A1
公开(公告)日：2008-10-30
申请号：US11742090
申请日：2007-04-30
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
摘要翻译：集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

84. 发明授权

US07342264B2 Memory cell and method for manufacturing the same 有权
标题翻译：存储单元及其制造方法
公开(公告)号：US07342264B2
公开(公告)日：2008-03-11
申请号：US11302738
申请日：2005-12-13
申请人： Tzu-Hsuan Hsu , Chao-I Wu , Ming-Hsiu Lee
发明人： Tzu-Hsuan Hsu , Chao-I Wu , Ming-Hsiu Lee
IPC分类号： H01L29/80 , H01L29/76
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/7851 , H01L29/7853 , H01L29/7923
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储单元包括跨门，载流子俘获结构和至少两个源/漏区。跨门位于基板上，跨越垂直翅片结构。载体捕获结构位于跨门和衬底之间，其中载流子俘获结构包括直接与跨骑门接触的捕获层和位于俘获层和基底之间的隧道层。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

85. 发明授权

US07266014B2 Method of operating non-volatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US07266014B2
公开(公告)日：2007-09-04
申请号：US11161359
申请日：2005-08-01
申请人： Chao-I Wu , Ming-Hsiu Lee
发明人： Chao-I Wu , Ming-Hsiu Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/18
摘要： A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method is carried out, a ultraviolet is irradiated to the non-volatile memory to inject electrons into the charge trapping layer to erase the non-volatile memory, and a negative voltage is applied to the gate conductive layer and a positive voltage is applied to the drain region to program the non-volatile memory by band-to-band induced hot hole injection.
摘要翻译：提供了一种操作非易失性存储器的方法，其中非易失性存储器至少包括：通过层叠隧穿介电层，电荷俘获层，电介质层和栅极导电层顺序地形成的栅极结构，以及源极区域和漏极区域。当执行操作方法时，紫外线照射到非易失性存储器以将电子注入电荷捕获层以擦除非易失性存储器，并且向栅极导电层施加负电压，并且正电压为施加到漏极区域以通过频带带诱导的热空穴注入对非易失性存储器进行编程。

86. 发明申请

US20070132000A1 Memory cell and method for manufacturing the same 有权
标题翻译：存储单元及其制造方法
公开(公告)号：US20070132000A1
公开(公告)日：2007-06-14
申请号：US11302738
申请日：2005-12-13
申请人： Tzu-Hsuan Hsu , Chao-I Wu , Ming-Hsiu Lee
发明人： Tzu-Hsuan Hsu , Chao-I Wu , Ming-Hsiu Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/7851 , H01L29/7853 , H01L29/7923
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储单元包括跨门，载流子俘获结构和至少两个源/漏区。跨门位于基板上，跨越垂直翅片结构。载体捕获结构位于跨门和衬底之间，其中载流子俘获结构包括直接与跨骑门接触的捕获层和位于俘获层和基底之间的隧道层。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

87. 发明授权

US07038928B1 Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods 有权
标题翻译：确定操作双侧非易失性存储器的最佳电压的方法和操作方法
公开(公告)号：US07038928B1
公开(公告)日：2006-05-02
申请号：US10991537
申请日：2004-11-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
IPC分类号： G11C17/00
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/26
摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm (=I2(VgO)−I1(VgO)).
摘要翻译：描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是测量，其中Vg是栅极电压。绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

88. 发明授权

US09000412B2 Switching device and operating method for the same and memory array 有权
标题翻译：相同和存储器阵列的开关器件和操作方法
公开(公告)号：US09000412B2
公开(公告)日：2015-04-07
申请号：US13561558
申请日：2012-07-30
申请人： Wei-Chih Chien , Feng-Ming Lee , Ming-Hsiu Lee
发明人： Wei-Chih Chien , Feng-Ming Lee , Ming-Hsiu Lee
IPC分类号： H01L29/06 , G11C13/00 , H01L43/02 , H01L45/00
CPC分类号： G11C13/0002 , G11C13/003 , H01L27/2409 , H01L43/02 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.
摘要翻译：提供了一种切换装置及其操作方法及其存储器阵列。开关装置包括第一固体电解质，第二固体电解质和开关层。开关层与第一固体电解质和第二固体电解质相邻。

89. 发明授权

US08937291B2 Three-dimensional array structure for memory devices 有权
标题翻译：用于存储器件的三维阵列结构
公开(公告)号：US08937291B2
公开(公告)日：2015-01-20
申请号：US13528754
申请日：2012-06-20
申请人： Ming-Hsiu Lee , Wei-Chih Chien
发明人： Ming-Hsiu Lee , Wei-Chih Chien
IPC分类号： H01L47/00 , H01L29/06
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/1022
摘要： A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.
摘要翻译：所公开的存储器件包括三维阵列结构，其包括设置在存储层之间的存储层和晶体管结构。每个存储器层连接到公共电极，并且每个晶体管结构包括共享公共列结构和公共基极结构的晶体管。晶体管还各自包括通过公共基底结构与公共柱结构间隔开的连接器结构。

90. 发明授权

US08824188B2 Operating method for memory device and memory array and operating method for the same 有权
标题翻译：存储器件和存储器阵列的操作方法和操作方法相同
公开(公告)号：US08824188B2
公开(公告)日：2014-09-02
申请号：US13567750
申请日：2012-08-06
申请人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
发明人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/004 , G11C2013/0047 , G11C2013/0052 , G11C2013/0073 , G11C2213/77
摘要： An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.
摘要翻译：提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。存储器件的操作方法包括以下步骤。使存储器件处于置位状态。用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。读取设置状态的存储器件。一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。将恢复的偏置电压施加到存储器件。在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

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