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81. 发明授权

US07366033B2 3-level non-volatile semiconductor memory device and method of driving the same 失效
标题翻译： 3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US07366033B2
公开(公告)日：2008-04-29
申请号：US11460580
申请日：2006-07-27
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

82. 发明申请

US20080074923A1 FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20080074923A1
公开(公告)日：2008-03-27
申请号：US11855978
申请日：2007-09-14
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483
摘要： A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.
摘要翻译：公开了一种闪存器件及其编程方法。闪存器件包括由多个位线和多个字线相交的存储器单元的阵列。页面缓冲电路包括耦合到偶数虚拟位线和奇数虚拟位线的多个锁存器。页面缓冲器电路被配置为响应于选择电路将数据加载到存储器单元阵列中，该选择电路被构造为将至少一些位线电耦合到页缓冲器电路的多个锁存器。

83. 发明申请

US20080013377A1 Non-volatile memory devices including dummy word lines and related structures and methods 有权
标题翻译：包括虚拟字线和相关结构和方法的非易失性存储器件
公开(公告)号：US20080013377A1
公开(公告)日：2008-01-17
申请号：US11729169
申请日：2007-03-28
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。还讨论了相关方法。

84. 发明申请

US20080007999A1 Nonvolatile memory device with NAND cell strings 有权
标题翻译：具有NAND单元串的非易失性存储器件
公开(公告)号：US20080007999A1
公开(公告)日：2008-01-10
申请号：US11657696
申请日：2007-01-25
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/3418
摘要： A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.
摘要翻译：非易失性存储器件包括存储单元阵列，其中多个存储单元晶体管被分成多个擦除块。多个擦除块通过虚拟字线彼此分离。在多个块之一的擦除操作期间，以耦合禁止电压驱动将多个块中的一个与其它擦除块分开的虚拟字线。

85. 发明申请

US20070257302A1 Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件及其形成方法
公开(公告)号：US20070257302A1
公开(公告)日：2007-11-08
申请号：US11797401
申请日：2007-05-03
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

86. 发明申请

US20070075336A1 Flash memory devices having shared sub active regions and methods of fabricating the same 有权
标题翻译：具有共享子有源区的闪存器件及其制造方法
公开(公告)号：US20070075336A1
公开(公告)日：2007-04-05
申请号：US11376371
申请日：2006-03-15
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L27/10
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

87. 发明申请

US20060208338A1 Nonvolatile memory devices and methods of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20060208338A1
公开(公告)日：2006-09-21
申请号：US11375983
申请日：2006-03-15
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

88. 发明申请

US20060208302A1 Non-volatile memory device having charge trap layer and method of fabricating the same 审中-公开
标题翻译：具有电荷陷阱层的非易失性存储器件及其制造方法
公开(公告)号：US20060208302A1
公开(公告)日：2006-09-21
申请号：US11354535
申请日：2006-02-15
申请人： Yoo-Cheol Shin , Jung-Dal Choi , Ki-Tae Park , Jong-Sun Sel
发明人： Yoo-Cheol Shin , Jung-Dal Choi , Ki-Tae Park , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L29/792
摘要： A non-volatile memory device having a charge trap layer and a method of fabricating the same are provided. The non-volatile memory device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate field region to define the active region and has a protrusion higher than a top surface of the semiconductor substrate active region. A memory storage pattern is formed which crosses and extends from the semiconductor substrate active region to cover sidewalls of the protrusion of the trench isolation layer. A gate electrode is formed on the memory storage pattern and extends upward from the trench isolation layer.
摘要翻译：提供了具有电荷陷阱层的非易失性存储器件及其制造方法。非易失性存储器件包括具有有源区和与有源区接触的场区的半导体衬底。沟槽隔离层形成在半导体衬底场区内，以限定有源区，并具有高于半导体衬底有源区的顶表面的突起。形成存储器存储图案，其跨越并从半导体衬底有源区域延伸以覆盖沟槽隔离层的突起的侧壁。栅电极形成在存储器存储图案上并从沟槽隔离层向上延伸。

89. 发明授权

US07084440B2 Integrated circuit layout and a semiconductor device manufactured using the same 有权
公开(公告)号：US07084440B2
公开(公告)日：2006-08-01
申请号：US10376465
申请日：2003-02-28
申请人： Jong-Sun Sel , Hong-Soo Kim , Jung-Dal Choi
发明人： Jong-Sun Sel , Hong-Soo Kim , Jung-Dal Choi
IPC分类号： H01L27/10 , H01L29/73 , H01L23/58 , H01L29/76
CPC分类号： H01L27/0207 , H01L27/115
摘要： An integrated circuit layout and a semiconductor device manufactured using the same are provided. According to one embodiment, a semiconductor device has a substrate and a plurality of bar type patterns on the substrate. The bar type patterns are substantially parallel to each other. At least one of the bar type patterns includes first and second ends and a middle part therebetween. The bar type patterns has an overhang at the first end thereof. The bar type patterns may be gate patterns, bit line patterns or active patterns.

90. 发明申请

US20060093966A1 Semiconductor devices with sidewall conductive patterns methods of fabricating the same 有权
标题翻译：具有侧壁导电图案的半导体器件制造方法
公开(公告)号：US20060093966A1
公开(公告)日：2006-05-04
申请号：US11241458
申请日：2005-09-30
申请人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
发明人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
IPC分类号： G03F7/00
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11529
摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
摘要翻译：公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。下导电图案在基板上。绝缘图案位于下导电图案上。上导电图案位于与下导电图案相对的绝缘图案上。侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。侧壁导电图形电连接上导电图案和下导电图案。下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

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