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81. 发明授权

US07137120B2 Dynamic diagnostic program for determining thread wait time 有权
公开(公告)号：US07137120B2
公开(公告)日：2006-11-14
申请号：US10022982
申请日：2001-12-17
申请人： William Joseph Armstrong , Ryan Harvey Bishop , Michael Brian Brutman , Chris Francois , Richard Karl Kirkman , Jay Paul Kurtz , Henry Joseph May , Naresh Nayar , Dennis A. Towne
发明人： William Joseph Armstrong , Ryan Harvey Bishop , Michael Brian Brutman , Chris Francois , Richard Karl Kirkman , Jay Paul Kurtz , Henry Joseph May , Naresh Nayar , Dennis A. Towne
IPC分类号： G06F9/46 , G06F9/45 , G06F15/16 , G06F17/30 , G06F19/00
CPC分类号： G06F11/3419 , G06F11/3404 , G06F11/3466 , Y10S707/99938 , Y10S707/99953
摘要： Diagnostic data, such as a time increment corresponding to how long a thread waits to access a shared resource, is stored within a predetermined location in a data structure, such as a hash bucket in a hash table. The location is preferably correlated to the resource such that a display of the diagnostic data may be tailored to reflect a user-specified relationship between the data and resource.

82. 发明申请

US20060253682A1 Managing computer memory in a computing environment with dynamic logical partitioning 审中-公开
标题翻译：在具有动态逻辑分区的计算环境中管理计算机内存
公开(公告)号：US20060253682A1
公开(公告)日：2006-11-09
申请号：US11122801
申请日：2005-05-05
申请人： William Armstrong , Richard Arndt , Michael Corrigan , David Engebretsen , Timothy Marchini , Naresh Nayar
发明人： William Armstrong , Richard Arndt , Michael Corrigan , David Engebretsen , Timothy Marchini , Naresh Nayar
IPC分类号： G06F12/00
CPC分类号： G06F3/065 , G06F3/0611 , G06F3/0673 , G06F12/1036 , G06F12/109
摘要： Managing computer memory in a computer with dynamic logical partitioning that operates transparently with respect to operating systems in logical partitions. Exemplary methods, systems, and products are described for managing computer memory in a computer with dynamic logical partitioning that include copying by a hypervisor, from page frames in one logical memory block (“LMB”) of a logical partition (“LPAR”) to page frames outside the LMB, contents of page frames having page frame numbers in a page table for an operating system in the LPAR. Embodiments typically include storing new page frame numbers in the page table, including storing by the hypervisor, for each page frame whose contents are copied, a new page frame number that identifies the page frame to which contents are copied. In typical embodiments, copying contents of page frames and storing new page frame numbers are carried out transparently with respect to the operating system.
摘要翻译：在具有相对于逻辑分区中的操作系统透明运行的动态逻辑分区的计算机中管理计算机内存。描述了用于在具有动态逻辑划分的计算机中管理计算机存储器的示例性方法，系统和产品，其包括由管理程序从逻辑分区（“LPAR”）的一个逻辑存储块（“LMB”）中的页面帧到在LMB之外的页框，在LPAR中的操作系统的页表中具有页框号的页框内容。实施例通常包括在页面表中存储新的页面帧号码，包括由管理程序存储针对其内容被复制的每个页面帧的新的页面帧号，其标识内容被复制到的页面帧。在典型的实施例中，相对于操作系统透明地执行复印页面的内容和存储新的页面帧号码。

83. 发明授权

US07111200B2 Apparatus and method for debugging a logical partition 有权
标题翻译：用于调试逻辑分区的装置和方法
公开(公告)号：US07111200B2
公开(公告)日：2006-09-19
申请号：US10418323
申请日：2003-04-17
申请人： Troy David Armstrong , William Joseph Armstrong , Tracy Bashore , George F. Eckman , Naresh Nayar
发明人： Troy David Armstrong , William Joseph Armstrong , Tracy Bashore , George F. Eckman , Naresh Nayar
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/362
摘要： A logical partition debugger allows debugging one logical partition in a computer system without requiring the shutdown of other logical partitions. The logical partition debugger is implemented in software in the partition manager. The logical partition debugger provides many common debug functions known in existing hardware and software debuggers, but does so in a manner that only the partition being debugged is affected.
摘要翻译：逻辑分区调试器允许在计算机系统中调试一个逻辑分区，而不需要关闭其他逻辑分区。逻辑分区调试器在分区管理器中的软件中实现。逻辑分区调试器提供了现有硬件和软件调试器中已知的许多常见的调试功能，但这样做的方式只有被调试的分区受到影响。

84. 发明授权

US07058782B2 Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism 失效
标题翻译：用于协调动态内存释放与冗余位线转向机制的方法和装置
公开(公告)号：US07058782B2
公开(公告)日：2006-06-06
申请号：US10631067
申请日：2003-07-31
申请人： Daniel James Henderson , Alongkorn Kitamorn , Wayne L. Lemmon , Naresh Nayar , Ravi A. Shankar
发明人： Daniel James Henderson , Alongkorn Kitamorn , Wayne L. Lemmon , Naresh Nayar , Ravi A. Shankar
IPC分类号： G06F12/00
CPC分类号： G11C29/42 , G06F11/106 , G11C29/70 , G11C2029/0409
摘要： A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctable errors. When a correctable error is encountered during runtime, and the correctable error is determined to be persistent, then dynamic memory page deallocation is requested of a hypervisor. The determination of persistence is based on a history CE table that is populated by the operation of the memory scrubbing and redundant bit line steering mechanism of a service processor. Thus, only those correctable errors that persist for longer than one memory scrubbing cycle are subject to memory page deallocation.
摘要翻译：提供了一种用于与冗余位线转向机构协调动态存储器页面解除分配的方法和装置。利用该方法和装置，与处理运行时可校正错误的通知并行执行存储器擦除和冗余位线转向操作。当在运行时遇到可纠正的错误，并且确定可纠正的错误是持久的，则请求虚拟机管理程序的动态内存页解除分配。持久性的确定基于由服务处理器的存储器擦除和冗余位线转向机制的操作填充的历史CE表。因此，只有那些持续时间超过一个内存擦除周期的可纠正错误才会受到内存页解除分配。

85. 发明授权

US06976100B2 Autonomic I/O adapter response performance optimization using polling 失效
标题翻译：自适应I / O适配器响应性能优化使用轮询
公开(公告)号：US06976100B2
公开(公告)日：2005-12-13
申请号：US10424198
申请日：2003-04-25
申请人： Shelly Marie Dirstine , Naresh Nayar , Gregory Michael Nordstrom
发明人： Shelly Marie Dirstine , Naresh Nayar , Gregory Michael Nordstrom
IPC分类号： G06F3/00
CPC分类号： G06F9/546 , G06F9/4881 , G06F2209/548
摘要： Methods, systems, and articles of manufacture for communicating with an I/O processor (IOP) are provided. Polling of message queue pointers is utilized to detect the occurrence of certain message queue related events, rather than rely on interrupts generated by the IOP. The polling may decrease the disruptive effects of IOP generated interrupts. In an effort to minimize the latency associated with detecting IOP related events, the polling may be initiated frequently by an operating system task dispatcher. In an effort to minimize context switches, the task dispatcher may schedule the processing of upstream messages detected while polling to coincide with naturally occurring task swaps.
摘要翻译：提供了与I / O处理器（IOP）通信的方法，系统和制品。消息队列指针的轮询用于检测某些消息队列相关事件的发生，而不是依赖于IOP生成的中断。轮询可能会减少IOP产生的中断的破坏性影响。为了最小化与检测IOP相关事件相关联的延迟，轮询可以由操作系统任务分派器频繁地启动。为了最小化上下文切换，任务调度器可以调度在轮询期间检测到的上行消息的处理以与自然发生的任务交换重合。

86. 发明授权

US06467007B1 Processor reset generated via memory access interrupt 失效
标题翻译：通过存储器访问中断产生处理器复位
公开(公告)号：US06467007B1
公开(公告)日：2002-10-15
申请号：US09314769
申请日：1999-05-19
申请人： Troy David Armstrong , William Joseph Armstrong , Naresh Nayar , Kenneth Charles Vossen
发明人： Troy David Armstrong , William Joseph Armstrong , Naresh Nayar , Kenneth Charles Vossen
IPC分类号： G06F1324
CPC分类号： G06F11/0712 , G06F1/24 , G06F11/073 , G06F11/0793
摘要： An apparatus, program product, and method utilize a memory access interrupt to effect a reset of a processor in a multi-processor environment. Specifically, a source processor is permitted to initiate a reset of a target processor simply by generating both a reset request and a memory access interrupt for the target processor. The target processor is then specifically configured to detect the presence of a pending reset request during handing of the memory access interrupt, such that the target processor will perform a reset operation responsive to detection of such a request.
摘要翻译：一种装置，程序产品和方法利用存储器访问中断来实现多处理器环境中的处理器的复位。具体来说，源处理器被简单地通过产生目标处理器的复位请求和存储器访问中断来允许目标处理器的复位。然后，目标处理器被特别地配置成在处理存储器访问中断期间检测到待处理复位请求的存在，使得目标处理器将响应于对这种请求的检测而执行复位操作。

87. 发明授权

US09454405B2 Paging partition arbitration of paging devices to shared memory partitions 有权
标题翻译：寻呼设备的寻呼分区仲裁到共享内存分区
公开(公告)号：US09454405B2
公开(公告)日：2016-09-27
申请号：US12414441
申请日：2009-03-30
申请人： Richard L. Arndt , Carol B. Hernandez , Kyle A. Lucke , Timothy R. Marchini , Naresh Nayar , James A. Pafumi
发明人： Richard L. Arndt , Carol B. Hernandez , Kyle A. Lucke , Timothy R. Marchini , Naresh Nayar , James A. Pafumi
IPC分类号： G06F12/00 , G06F9/50 , G06F11/20
CPC分类号： G06F9/5077 , G06F11/2094
摘要： Disclosed is a computer implemented method, computer program product, and apparatus to establish at least one paging partition in a data processing system. The virtualization control point (VCP) reserves up to the subset of physical memory for use in the shared memory pool. The VCP configures at least one logical partition as a shared memory partition. The VCP assigns a paging partition to the shared memory pool. The VCP determines whether a user requests a redundant assignment of the paging partition to the shared memory pool. The VCP assigns a redundant paging partition to the shared memory pool, responsive to a determination that the user requests a redundant assignment. The VCP assigns a paging device to the shared memory pool. The hypervisor may transmit at least one paging request to a virtual asynchronous services interface configured to support a paging device stream.
摘要翻译：公开了一种在数据处理系统中建立至少一个寻呼分区的计算机实现方法，计算机程序产品和装置。虚拟化控制点（VCP）保留到用于共享内存池的物理内存子集。 VCP将至少一个逻辑分区配置为共享内存分区。 VCP将分页分区分配给共享内存池。 VCP确定用户是否请求分页分区的冗余分配给共享内存池。响应于确定用户请求冗余分配，VCP将冗余分页分区分配给共享内存池。 VCP将分页设备分配给共享内存池。管理程序可以向被配置为支持寻呼设备流的虚拟异步服务接口发送至少一个寻呼请求。

88. 发明授权

US09069598B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
标题翻译：提供逻辑分支与反映独家使用处理器核心的硬件线程特定信息
公开(公告)号：US09069598B2
公开(公告)日：2015-06-30
申请号：US13345002
申请日：2012-01-06
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
摘要翻译：用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器信息。如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行物理寄存器包含信息。

89. 发明授权

US08990816B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
公开(公告)号：US08990816B2
公开(公告)日：2015-03-24
申请号：US13452745
申请日：2012-04-20
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/52 , G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

90. 发明授权

US08832707B2 Tunable error resilience computing 有权
标题翻译：可调整的错误恢复能力计算
公开(公告)号：US08832707B2
公开(公告)日：2014-09-09
申请号：US12642908
申请日：2009-12-21
申请人： Daniel J. Henderson , Prabhakar N. Kudva , Naresh Nayar , Pia Naoko Sanda , David William Siegel , James Van Oosten , James Xenidis
发明人： Daniel J. Henderson , Prabhakar N. Kudva , Naresh Nayar , Pia Naoko Sanda , David William Siegel , James Van Oosten , James Xenidis
IPC分类号： G06F9/46 , G06F15/173 , G06F9/50
CPC分类号： G06F9/5027 , Y02D10/22
摘要： An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality if resources for completion of the task in accordance with a level of quality of service in a service level agreement.
摘要翻译：与任务相关联的描述符的属性通知运行时环境处理器将要运行的指令，以根据服务级别协议中的服务质量级别来调度多个用于完成任务的资源。

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