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81. 发明申请

US20100200937A1 METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 失效
标题翻译：具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构
公开(公告)号：US20100200937A1
公开(公告)日：2010-08-12
申请号：US12367759
申请日：2009-02-09
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/78 , H01L21/36
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

82. 发明授权

US07772016B2 Method for composition control of a metal compound film 失效
标题翻译：金属化合物膜的组成控制方法
公开(公告)号：US07772016B2
公开(公告)日：2010-08-10
申请号：US11696507
申请日：2007-04-04
申请人： Russell D. Allen , Stephen L. Brown , Alessandro C. Callegari , Michael P. Chudzik , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Russell D. Allen , Stephen L. Brown , Alessandro C. Callegari , Michael P. Chudzik , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/66
CPC分类号： G01N21/8422 , G01N21/59 , H01L22/12 , H01L22/20
摘要： Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.
摘要翻译：使用消光系数k的测量来有效且迅速地在线监测和/或控制金属膜组合物。消光系数对金属化合物的组成的依赖性的特征在于测量一系列具有不同组成的金属化合物的消光系数。然后将监测金属膜沉积在晶片上。测量晶片上的膜的消光系数k并提取膜组成参数。如果k在规范中，则可以继续进行晶片处理，或者可以从k的测量值中提取胶片中所需的组成变化，并且建立k对于超出规格k值的胶片组成的建立依赖性。

83. 发明申请

US20090212369A1 Gate Effective-Workfunction Modification for CMOS 有权
标题翻译：门有效功能修改CMOS
公开(公告)号：US20090212369A1
公开(公告)日：2009-08-27
申请号：US12037158
申请日：2008-02-26
申请人： Dae-Gyu Park , Michael P. Chudzik , Rashmi Jha , Siddarth A. Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Rashmi Jha , Siddarth A. Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/785
摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.
摘要翻译：公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

84. 发明申请

US20090181507A1 SIGE CHANNEL EPITAXIAL DEVELOPMENT FOR HIGH-K PFET MANUFACTURABILITY 失效
标题翻译：用于高K PFET制造商的信号通道外延开发
公开(公告)号：US20090181507A1
公开(公告)日：2009-07-16
申请号：US12014815
申请日：2008-01-16
申请人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
发明人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/823842 , H01L21/823878
摘要： A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.
摘要翻译：用于生长外延层的方法在衬底上图案掩模。掩模保护要形成N型场效应晶体管（NFET）的衬底的第一区域（N型区域），并露出衬底的第二区域（P型区域），其中P型场效应晶体管（PFET））将被形成。使用掩模，该方法可以仅在P型区域上外延生长硅锗层。然后去除掩模，并在N型区域和P型区域中对浅沟槽隔离（STI）沟槽进行图案化（使用不同的掩模）。该STI图案化工艺定位STI沟槽以便去除外延层的边缘。然后用隔离材料填充沟槽。最后，NFET形成为具有第一金属栅极，并且PFET形成为具有与第一金属栅极不同的第二金属栅极。第一金属门具有与第二金属栅极不同的功函数。

85. 发明申请

US20090152637A1 PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT 有权
标题翻译：具有定制电介质的PFET及相关方法和集成电路
公开(公告)号：US20090152637A1
公开(公告)日：2009-06-18
申请号：US11955491
申请日：2007-12-13
申请人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
发明人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/82385
摘要： A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.
摘要翻译：公开了一种具有由其栅极堆叠中的NFET阈值电压（Vt）功函数调谐层，相关方法和集成电路部分构成的定制电介质的PFET。在一个实施例中，PFET包括n型掺杂硅阱（N阱），栅堆叠，其包括：在N阱上的掺杂带工程化PFET阈值电压（Vt）功函数调谐层; 在掺杂带工程化的PFET Vt功函数调谐层之上的定制电介质层，由掺杂带工程化的PFET Vt功函数调谐层和n型场效应晶体管（NFET）阈值上的高介电常数层构成的调整后的介电层电压（Vt）工作功能调谐层在高介电常数层上; 和NFET Vt功能调谐层上的金属。

86. 发明申请

US20090108356A1 INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 失效
标题翻译：多金属门工作功能结构的整合方案
公开(公告)号：US20090108356A1
公开(公告)日：2009-04-30
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

87. 发明授权

US07459913B2 Methods for the determination of film continuity and growth modes in thin dielectric films 失效
标题翻译：薄介电膜中膜连续性和生长模式的测定方法
公开(公告)号：US07459913B2
公开(公告)日：2008-12-02
申请号：US10710947
申请日：2004-08-13
申请人： Michael P. Chudzik , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Joseph F. Shepard, Jr.
IPC分类号： G01N27/60 , G01R31/26 , G01R27/08
CPC分类号： H01L21/02263 , C23C16/45525 , C23C16/52 , H01L21/0228 , H01L21/314
摘要： A method for determining film continuity and growth modes in thin dielectric films includes: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison. The growth metric parameters may include thickness, time, precursor cycles, or temperature.
摘要翻译：用于确定薄介电膜中的膜连续性和生长模式的方法包括：使用生长度量的第一值将材料沉积在衬底上; 在所述材料的表面上沉积一定量的电荷; 重复地测量材料的表面电压，直到隧道开始，以提供Vtunnel（或Etunnel）值; 对生长度量的不同值重复上述步骤; 以及比较生长度量值的不同值的Vtunnel（或Etunnel）值，以提供衬底上材料的连续性的量度。材料的生长模式可以通过比较Vtunnel或Etunnel的每个生长度量曲线的一阶导数与生长指标，并检查比较结果的线性来确定。生长度量参数可以包括厚度，时间，前体循环或温度。

88. 发明授权

US07186625B2 High density MIMCAP with a unit repeatable structure 失效
标题翻译：具有单位可重复结构的高密度MIMCAP
公开(公告)号：US07186625B2
公开(公告)日：2007-03-06
申请号：US10709768
申请日：2004-05-27
申请人： Michael P. Chudzik , Louis L. Hsu , Joseph F. Shepard, Jr. , William R. Tonti
发明人： Michael P. Chudzik , Louis L. Hsu , Joseph F. Shepard, Jr. , William R. Tonti
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
摘要翻译：用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

89. 发明授权

US09029959B2 Composite high-k gate dielectric stack for reducing gate leakage 有权
标题翻译：用于减少栅极泄漏的复合高k栅极电介质堆叠
公开(公告)号：US09029959B2
公开(公告)日：2015-05-12
申请号：US13537101
申请日：2012-06-29
申请人： MaryJane Brodsky , Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Yanfeng Wang , Jinping Liu
发明人： MaryJane Brodsky , Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Yanfeng Wang , Jinping Liu
IPC分类号： H01L29/49 , H01L21/02 , H01L21/28 , H01L21/3115 , H01L21/8234 , H01L29/51
CPC分类号： H01L21/02321 , H01L21/28194 , H01L21/3115 , H01L21/823462 , H01L29/513 , H01L29/517
摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.
摘要翻译：复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

90. 发明授权

US08778750B2 Techniques for the fabrication of thick gate dielectric 失效
标题翻译：用于制造厚栅极电介质的技术
公开(公告)号：US08778750B2
公开(公告)日：2014-07-15
申请号：US13464966
申请日：2012-05-05
申请人： Eduard Albert Cartier , Michael P. Chudzik , Andreas Kerber , Siddarth Krishnan , Naim Moumen
发明人： Eduard Albert Cartier , Michael P. Chudzik , Andreas Kerber , Siddarth Krishnan , Naim Moumen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/76224
摘要： A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.
摘要翻译：一种制造CMOS器件的方法包括以下步骤。提供晶片。 STI用于在晶片中形成至少一个有效区域。氧化硅层沉积在覆盖有源区的晶片上。第一高k材料沉积在氧化硅层上。选择性地去除氧化硅层和第一高k材料的部分，使得氧化硅层和第一高k材料保留在有源区的一个或多个第一区上，并从一个或多个第二个活跃区域。在有源区域的一个或多个第一区域上并且在有源区域的一个或多个第二区域中的晶片的表面上沉积第二高k材料到第一高k材料上。还提供了CMOS器件。

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