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81. 发明授权

US06354133B1 Use of carbon nanotubes to calibrate conventional tips used in AFM 失效
标题翻译：使用碳纳米管校准AFM中使用的常规提示
公开(公告)号：US06354133B1
公开(公告)日：2002-03-12
申请号：US09729293
申请日：2000-12-04
申请人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
发明人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
IPC分类号： G01B528
CPC分类号： G01Q40/02 , G01Q40/00 , Y10S977/742 , Y10S977/842 , Y10S977/849 , Y10S977/85 , Y10S977/876 , Y10S977/901
摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.
摘要翻译：本发明提供了用于校准纳米测量装置的系统，方法和标准。本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。碳纳米管校准标准品的宽度以高精度已知。考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

82. 发明授权

US6093967A Self-aligned silicide contacts formed from deposited silicon 失效
标题翻译：由沉积硅形成的自对准硅化物触点
公开(公告)号：US6093967A
公开(公告)日：2000-07-25
申请号：US992573
申请日：1997-12-17
申请人： Yowjuang W. Liu , Mark S. Chang , Michael K. Templeton
发明人： Yowjuang W. Liu , Mark S. Chang , Michael K. Templeton
IPC分类号： H01L21/285 , H01L23/54 , H01L21/441
CPC分类号： H01L21/28518
摘要： Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.
摘要翻译：通过在衬底的有源区上沉积硅，在硅上沉积难熔金属，并加热硅和难熔金属，形成具有至少约等于栅极高度的高度的自对准硅化物触点。沉积的硅可以是非晶硅，在这种情况下，沉积温度可以低至580℃。如果沉积多晶硅，则沉积温度必须至少为620℃。

83. 发明授权

US06834158B1 Pinhole defect repair by resist flow 失效
标题翻译：针孔缺陷修复由抗流动
公开(公告)号：US06834158B1
公开(公告)日：2004-12-21
申请号：US09951473
申请日：2001-09-13
申请人： Michael K. Templeton
发明人： Michael K. Templeton
IPC分类号： F26B330
CPC分类号： B82Y15/00 , G03F7/40
摘要： According to one aspect of the present invention, pinhole defects in resist coatings are repaired by heating the resist briefly to induce the resist to flow and fill pinholes. The resist is brought to a temperature at or above that at which the resist flows for long enough to permit the resist to flow and fill pinhole defects, but not so long as to corrupt the resist pattern. The original resist pattern may be biased to allow for some flow during the pinhole repair process. The entire patterned resist may be heated at once, or it may be heated one portion at a time. The application of heat may optionally be limited to locations where pinhole defects are found. By means of the invention, very thin patterned resist coatings free from pinhole defects may be obtained.
摘要翻译：根据本发明的一个方面，抗蚀剂涂层中的针孔缺陷通过短暂加热抗蚀剂来引起抗蚀剂流动和填充针孔而被修复。使抗蚀剂达到等于或高于抗蚀剂流动的温度足够长以允许抗蚀剂流动并填充针孔缺陷，但不会损坏抗蚀剂图案。原始抗蚀剂图案可能被偏压以允许针孔修复过程中的一些流动。整个图案化的抗蚀剂可以一次加热，或者可以一次加热一部分。热的应用可以可选地限于找到针孔缺陷的位置。通过本发明，可以获得非常薄的图案化抗蚀剂涂层，其不存在针孔缺陷。

84. 发明授权

US06830389B2 Parallel plate development with the application of a differential voltage 失效
标题翻译：平行板开发应用差分电压
公开(公告)号：US06830389B2
公开(公告)日：2004-12-14
申请号：US09973034
申请日：2001-10-09
申请人： Michael K. Templeton
发明人： Michael K. Templeton
IPC分类号： G03B500
CPC分类号： G03F7/3007
摘要： A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. A differential voltage is applied to the developer plate and the wafer causing an electric field to be formed in the gap. Transportation of negatively charge photoresist material is facilitated by exposure to the electric field during the development process.
摘要翻译：提供了一种用于将显影剂施加到设置在半导体衬底上的光致抗蚀剂材料层的系统和方法。显影剂系统和方法采用具有多个用于分配显影剂的孔的显影剂板。优选地，显影剂板具有与晶片类似的形状的底表面。显影剂板设置在晶片上方并且在施加显影剂的过程中基本上和/或完全地包围晶片的顶表面。在晶片和显影剂板的底表面之间形成小的间隙。晶片和显影剂板形成平行板对，使得间隙可以制得足够小，使得显影剂流体快速填充间隙。对显影剂板和晶片施加差分电压，从而在间隙中形成电场。在显影过程中通过暴露于电场来促进负电荷光致抗蚀剂材料的传输。

85. 发明授权

US06752899B1 Acoustic microbalance for in-situ deposition process monitoring and control 失效
标题翻译：用于原位沉积过程监测和控制的声学微量天平
公开(公告)号：US06752899B1
公开(公告)日：2004-06-22
申请号：US10050499
申请日：2002-01-16
申请人： Bhanwar Singh , Arvind Halliyal , Michael K. Templeton
发明人： Bhanwar Singh , Arvind Halliyal , Michael K. Templeton
IPC分类号： H01L2100
CPC分类号： H01L21/67253 , C23C14/545 , C23C16/52
摘要： The invention provides a system and process for depositing films, wherein an acoustic microbalance is used for process monitoring and/or control. The acoustic microbalance is placed in a deposition chamber and may optionally be mounted on a semiconductor substrate, such as a silicon wafer, on which a film is being deposited. Data from the acoustic microbalance is employed to detect a process endpoint, determine an adjustment to process conditions for a subsequent batch, and/or provide feedback control over current process conditions. One aspect of the invention involves the application of a model or database to correct for differences between the extent of deposition on an acoustic microbalance cantilever and the extent of deposition on a substrate being processed. Another aspect of the invention takes a probabilistic approach to employing acoustic microbalance data. The acoustic microbalance data is employed, optionally together with other process data, as evidence in a probabilistic dependancy model that infers the process state and/or predicts a process outcome.
摘要翻译：本发明提供一种用于沉积膜的系统和方法，其中使用声学微量天平进行过程监测和/或控制。声学微量天平被放置在沉积室中，并且可以可选地安装在其上沉积有膜的半导体衬底（例如硅晶片）上。来自声学微量天平的数据用于检测过程终点，确定对后续批次的处理条件的调整，和/或提供关于当前工艺条件的反馈控制。本发明的一个方面涉及应用模型或数据库来校正声学微平衡悬臂上的沉积程度与正在处理的基底上的沉积程度之间的差异。本发明的另一方面采用使用声学微量天平数据的概率方法。声学微量天平数据可选地与其他过程数据一起被用作推理过程状态和/或预测过程结果的概率依赖模型中的证据。

86. 发明授权

US06513996B1 Integrated equipment to drain water-hexane developer for pattern collapse 失效
标题翻译：集成设备排出水 - 己烷显影剂，用于图案塌陷
公开(公告)号：US06513996B1
公开(公告)日：2003-02-04
申请号：US10050436
申请日：2002-01-16
申请人： Ramkumar Subramanian , Michael K. Templeton , Bhanwar Singh
发明人： Ramkumar Subramanian , Michael K. Templeton , Bhanwar Singh
IPC分类号： G03B500
CPC分类号： G03F7/3021
摘要： One aspect of the present invention relates to a method and an apparatus for rinsing a substrate during a development process to mitigate pattern collapse. The apparatus includes a bath chamber; a substrate holder disposed in the bath chamber for holding the substrate having a resist pattern formed thereon; a first nozzle for dispensing a first rinsing solution having a first density and first surface tension into the bath chamber; a second nozzle for dispensing a second rinsing solution having a second density and second surface tension, which is less than the first rinsing solution, into the bath chamber; a drain disposed in a bottom portion of the bath chamber; and a controlling system operatively coupled to the first nozzle, the second nozzle and the drain designed to regulate and coordinate the operation of the first nozzle, the second nozzle and the drain.
摘要翻译：本发明的一个方面涉及一种用于在显影过程中漂洗衬底以减轻图案崩溃的方法和装置。该装置包括浴室; 设置在所述浴室中用于保持形成有抗蚀剂图案的所述基板的基板保持架; 用于将具有第一密度和第一表面张力的第一冲洗溶液分配到所述浴室中的第一喷嘴; 第二喷嘴，用于将具有小于第一冲洗溶液的第二密度和第二表面张力的第二冲洗溶液分配到浴室中; 排水口，其设置在所述浴室的底部; 以及可操作地联接到第一喷嘴，第二喷嘴和排水口的设计用于调节和协调第一喷嘴，第二喷嘴和排水管的操作的控制系统。

87. 发明授权

US5920786A Method for fabricating shallow isolation trenches using angular photoresist profiles to create sloped isolation trench walls 失效
标题翻译：使用角度光致抗蚀剂轮廓制造浅隔离沟槽以产生倾斜的隔离沟壁的方法
公开(公告)号：US5920786A
公开(公告)日：1999-07-06
申请号：US60894
申请日：1998-05-14
申请人： Tuan D. Pham , Michael K. Templeton
发明人： Tuan D. Pham , Michael K. Templeton
IPC分类号： G03F7/00 , G03F7/20 , H01L21/3065 , H01L21/308 , H01L21/762 , H01L29/68 , G03C5/00 , G03F9/00
CPC分类号： H01L21/3086 , G03F7/0035 , G03F7/201 , H01L21/3065 , H01L21/76232
摘要： The present invention provides a method of constructing trenches for use in microelectronic circuit structures. A photolithographic method is used to create trenches with sloped walls shaping the photoresist masks into sloped profiles. These photoresist masks effectively shape the underlying substrate during subsequent etch steps producing sloped wall trenches. These trenches can be used as shallow trench isolation structures to isolate microelectronic circuit structures from each other.
摘要翻译：本发明提供一种构建用于微电子电路结构的沟槽的方法。使用光刻方法来产生具有将光致抗蚀剂掩模成形为倾斜轮廓的倾斜壁的沟槽。这些光致抗蚀剂掩模在随后的蚀刻步骤中有效地塑造下面的衬底，产生倾斜的壁沟槽。这些沟槽可以用作浅沟槽隔离结构，以隔离微电子电路结构。

88. 发明授权

US07100826B1 Barcode marking of wafer products for inventory control 有权
标题翻译：晶圆产品条码标记库存控制
公开(公告)号：US07100826B1
公开(公告)日：2006-09-05
申请号：US09817615
申请日：2001-03-26
申请人： Khoi A. Phan , Michael K. Templeton , Bhanwar Singh
发明人： Khoi A. Phan , Michael K. Templeton , Bhanwar Singh
IPC分类号： G06F19/00 , G06F17/00
CPC分类号： G06Q10/087
摘要： A system for performing inventory control for wafers, unpackaged integrated circuits and packaged integrated circuits is provided. The system includes barcode readers, sorters and transporters operable to locate and relocate wafers, unpackaged circuits and packaged circuits. The system further includes a feedback system for feeding back information generated by the barcode readers, sorters, transporters and/or manufacturing devices associated with the wafers, unpackaged circuits and packaged circuits. The system further provides for generating Electronic Data Interchange (EDI) data that can be transmitted to wafer suppliers and employed in controlling wafer ordering, purchasing, processing and returning.
摘要翻译：提供了一种用于对晶片进行库存控制的系统，未封装的集成电路和封装的集成电路。该系统包括条形码读取器，分拣机和转运器，可操作以定位和重新定位晶片，未封装的电路和封装电路。该系统还包括反馈系统，用于反馈由条形码阅读器，分拣机，转运器和/或与晶片相关联的制造装置产生的信息，未包装的电路和封装的电路。该系统进一步提供了可以传输到晶圆供应商的电子数据交换（EDI）数据，并用于控制晶圆订购，采购，处理和退货。

89. 发明授权

US06688784B1 Parallel plate development with multiple holes in top plate for control of developer flow and pressure 有权
标题翻译：平行板开发，顶板上有多个孔，用于控制显影剂的流动和压力
公开(公告)号：US06688784B1
公开(公告)日：2004-02-10
申请号：US09974620
申请日：2001-10-10
申请人： Michael K. Templeton
发明人： Michael K. Templeton
IPC分类号： G03D504
CPC分类号： G03D5/04 , Y10S134/902
摘要： A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a application apertures for dispensing developer and a plurality of exit apertures for allowing excess developer to be removed from between the developer plate and the photoresist material layer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap with excess developer exiting through the exit apertures.
摘要翻译：提供了一种用于将显影剂施加到设置在半导体衬底上的光致抗蚀剂材料层的系统和方法。显影剂系统和方法采用具有多个用于分配显影剂的施加孔的显影剂板和用于允许从显影剂板和光致抗蚀剂材料层之间移除多余显影剂的多个出口孔的显影剂板。优选地，显影剂板具有与晶片类似的形状的底表面。显影剂板设置在晶片上方并且在施加显影剂的过程中基本上和/或完全地包围晶片的顶表面。在晶片和显影剂板的底表面之间形成小的间隙。晶片和显影剂板形成平行板对，使得间隙可以制得足够小，使得显影剂流体通过出射孔离开的过量显影剂快速填充间隙。

90. 发明授权

US06664191B1 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
标题翻译：非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间
公开(公告)号：US06664191B1
公开(公告)日：2003-12-16
申请号：US09973131
申请日：2001-10-09
申请人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
发明人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
IPC分类号： H01L21302
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/76229 , H01L21/76838 , H01L27/11531 , Y10S438/975
摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.
摘要翻译：提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。第一多晶硅层沉积在覆盖STI区域的衬底上。然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

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