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81. 发明授权

US06753701B2 Data-sampling strobe signal generator and input buffer using the same 有权
标题翻译：数据采样选通信号发生器和输入缓冲器使用相同
公开(公告)号：US06753701B2
公开(公告)日：2004-06-22
申请号：US10138268
申请日：2002-05-06
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H03K1900
CPC分类号： G11C7/1084 , G11C7/1078
摘要： A data-sampling strobe signal generator and an input buffer using the same. The data-sampling strobe signal includes a intermediate signal generator, a comparison circuit and a logic circuit. The intermediate signal generator compares non-inverting/inverting strobe signals and generates an intermediate signal based on the comparison result. The comparison circuit compares a reference voltage with the non-inverting strobe signal and the inverting strobe signal, respectively, and outputs a control signal. The control signal is enabled when one of the non-inverted/inverting strobe signals is higher than the reference voltage and the other is lower than the reference voltage, and disabled when the non-inverting/inverting strobe signals are the same logical level. The logic circuit receives the intermediate signal and the control signal and generates the data-sampling strobe signal from the intermediate signal when the control signal is enabled. In addition, the data-sampling strobe signal is a constant logic level when the control signal is disabled.
摘要翻译：数据采样选通信号发生器和使用其的输入缓冲器。数据采样选通信号包括中间信号发生器，比较电路和逻辑电路。中间信号发生器比较非倒相/反相选通信号，并根据比较结果生成中间信号。比较电路分别比较参考电压与反相选通信号和反相选通信号，并输出控制信号。当非反相/反相选通信号之一高于参考电压而另一个低于参考电压时，控制信号被使能，当非反相/反相选通信号是相同的逻辑电平时禁止。当控制信号使能时，逻辑电路接收中间信号和控制信号，并从中间信号产生数据采样选通信号。此外，当禁止控制信号时，数据采样选通信号是一个恒定的逻辑电平。

82. 发明授权

US06605511B2 Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation 失效
标题翻译：形成用于闪存技术电路的氮化隧道氧化物屏障的方法和STI和LOCOS隔离
公开(公告)号：US06605511B2
公开(公告)日：2003-08-12
申请号：US10295738
申请日：2002-11-15
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L218234
CPC分类号： H01L21/76202 , H01L21/76224 , H01L27/1052 , Y10S438/981
摘要： A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
摘要翻译：提供了一种通过首先使用硬掩模创建浅沟槽隔离来制造在外围区域中具有浅沟槽隔离和芯区域中的LOCOS隔离的改进的闪速存储器件的方法; 然后创建LOCOS隔离; 并随后蚀刻以除去桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化隧道氧化物层。使用硬掩模来防止栅极氧化物层的氮化物污染。

83. 发明授权

US06509232B1 Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device 有权
标题翻译：闪存器件的核心和周边区域内的STI（浅沟槽隔离）结构的形成
公开(公告)号：US06509232B1
公开(公告)日：2003-01-21
申请号：US09969573
申请日：2001-10-01
申请人： Unsoon Kim , Mark S. Chang , Yider Wu , Chi Chang , Angela Hui , Yu Sun
发明人： Unsoon Kim , Mark S. Chang , Yider Wu , Chi Chang , Angela Hui , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.
摘要翻译：形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的。沉积沟槽电介质材料以填充STI开口。此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

84. 发明授权

US06429108B1 Non-volatile memory device with encapsulated tungsten gate and method of making same 有权
标题翻译：具有封装钨栅的非易失性存储器件及其制造方法
公开(公告)号：US06429108B1
公开(公告)日：2002-08-06
申请号：US09652136
申请日：2000-08-31
申请人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
发明人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
IPC分类号： H01L213205
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11543 , H01L29/42324 , H01L29/66825
摘要： A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.
摘要翻译：通过将MOS晶体管和浮置栅极存储单元中的每一个的钨栅极电极接触封装在氮化硅封盖和侧壁层上，可制造钨栅极MOS晶体管和用于快闪EEPROM器件的存储单元，从而防止随后的处理过程中的有害氧化氧化环境中的高温。

85. 发明授权

US06346467B1 Method of making tungsten gate MOS transistor and memory cell by encapsulating 有权
标题翻译：通过封装制造钨栅MOS晶体管和存储单元的方法
公开(公告)号：US06346467B1
公开(公告)日：2002-02-12
申请号：US09649027
申请日：2000-08-28
申请人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
发明人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
IPC分类号： H01L213205
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.
摘要翻译：通过用氮化硅封盖和侧壁层封装MOS晶体管和浮动栅极存储单元中的每一个的钨栅极电极接触，制造了用于快闪EEPROM器件的钨栅MOS晶体管和存储单元。本发明的方法有利地防止在高温和氧化环境中的后续处理期间的有害氧化。

86. 发明授权

US06284600B1 Species implantation for minimizing interface defect density in flash memory devices 有权
标题翻译：用于最小化闪存器件中的界面缺陷密度的物种植入
公开(公告)号：US06284600B1
公开(公告)日：2001-09-04
申请号：US09609468
申请日：2000-07-03
申请人： Yider Wu , Mark T. Ramsbey , Chi Chang , Yu Sun , Tuan Duc Pham , Jean Y. Yang
发明人： Yider Wu , Mark T. Ramsbey , Chi Chang , Yu Sun , Tuan Duc Pham , Jean Y. Yang
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.
摘要翻译：将诸如氮的预定物质放置在闪存存储器件的控制电介质结构的位线结和电介质层之间的界面处，以通过在编程或擦除操作期间最小化界面缺陷的形成来最小化这种界面的劣化闪存设备。将诸如氮的预定物质注入到闪速存储器件的位线结中。执行加热半导体晶片的热处理，使得在热处理期间注入到半导体晶片内的预定物质例如氮漂移到位线结与控制电介质结构之间的界面。在闪存器件的编程或擦除操作期间，预定种类例如接口处的氮使界面缺陷的形成最小化，从而使界面的时效性降低。

87. 发明授权

US06252803B1 Automatic program disturb with intelligent soft programming for flash cells 有权
标题翻译：自动程序干扰与闪存单元的智能软编程
公开(公告)号：US06252803B1
公开(公告)日：2001-06-26
申请号：US09692881
申请日：2000-10-23
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
IPC分类号： G11C1616
CPC分类号： G11C16/16
摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
摘要翻译：提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。擦除脉冲被施加到多个存储单元。多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。重复此循环，直到所有的单元格都被验证为不被过高。多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。重复此循环，直到所有单元格都被验证为不被忽略。在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

88. 发明授权

US6001713A Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中的浮栅和互聚电介质层中形成富氮区的方法
公开(公告)号：US6001713A
公开(公告)日：1999-12-14
申请号：US154074
申请日：1998-09-16
申请人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
发明人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
IPC分类号： H01L21/28 , H01L21/265
CPC分类号： H01L21/28273
摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.
摘要翻译：提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。这在浮动栅极内形成初始氮浓度分布。然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

89. 发明授权

US5933730A Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method 失效
标题翻译：形成自对准源之后的间隔物形成和源保护的方法以及通过这种方法提供的装置
公开(公告)号：US5933730A
公开(公告)日：1999-08-03
申请号：US813562
申请日：1997-03-07
申请人： Yu Sun , Chi Chang , Mark T. Ramsbey
发明人： Yu Sun , Chi Chang , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.
摘要翻译：本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

90. 发明授权

US5805502A System for constant field erasure in a FLASH EPROM 失效
标题翻译： FLASH EPROM中常量字段擦除的系统
公开(公告)号：US5805502A
公开(公告)日：1998-09-08
申请号：US795024
申请日：1997-02-04
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

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