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81. 发明申请

US20140217553A1 TEMPLATE LAYERS FOR HETEROEPITAXIAL DEPOSITION OF III NITRIDE SEMICONDUCTOR MATERIALS USING HVPE PROCESSES 有权
标题翻译：使用HVPE工艺的III型氮化物半导体材料的异相沉积的模板层
公开(公告)号：US20140217553A1
公开(公告)日：2014-08-07
申请号：US13989004
申请日：2011-11-23
申请人： Chantal Arena , Ronald Thomas Bertram, JR. , Ed Lindow , Subhash Mahajan , Ilsu Han
发明人： Chantal Arena , Ronald Thomas Bertram, JR. , Ed Lindow , Subhash Mahajan , Ilsu Han
IPC分类号： H01L21/02 , H01L29/06
CPC分类号： H01L29/0665 , C30B25/183 , C30B29/403 , H01L21/0242 , H01L21/02458 , H01L21/02513 , H01L21/0254 , H01L21/0262 , H01L21/02667
摘要： Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.
摘要翻译：在衬底上沉积III族氮化物半导体材料的方法包括在成核HVPE工艺阶段中在衬底的表面上沉积III族氮化物半导体材料层，以形成具有包含至少一些非晶III族氮化物半导体材料的微结构的成核层。成核层可以退火以在衬底的表面上形成外延成核材料的晶体岛。外延成核材料岛可以在聚结HVPE工艺阶段中生长和聚结，以形成外延成核材料的成核模板层。成核模板层可以至少基本上覆盖基材的表面。另外的III族氮化物半导体材料可以在另外的HVPE工艺阶段中沉积在外延成核材料的成核模板层上。通过这种方法形成包含III族氮化物半导体材料的最终和中间结构。

82. 发明授权

US08692260B2 Method of forming a composite laser substrate 有权
标题翻译：形成复合激光基板的方法
公开(公告)号：US08692260B2
公开(公告)日：2014-04-08
申请号：US13001734
申请日：2009-09-21
申请人： Chantal Arena , Christiaan J. Werkhoven
发明人： Chantal Arena , Christiaan J. Werkhoven
IPC分类号： H01L29/20 , H01L33/30
CPC分类号： H01L33/00 , H01L21/0237 , H01L21/02458 , H01L21/02472 , H01L21/02483 , H01L21/02491 , H01L21/02502 , H01L21/0254 , H01S5/0215 , H01S5/0218
摘要： A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer formed on a support substrate, and a seed layer formed on the intermediate layer. An active device layer is grown or attached to the seed layer, or to a light confinement layer on the seed layer. The intermediate layer may be formed directly on the support layer, or may be formed by thinning an attached wafer of the intermediate material, which is then thinned to a desired thickness.
摘要翻译：公开了一种用于激光器件的复合衬底，其具有改进的波导特性，改进的晶格匹配，改进的热膨胀匹配和改善的导热性。复合基板具有形成在支撑基板上的中间层和形成在中间层上的种子层。活性器件层生长或附着到种子层或种子层上的光限制层。中间层可以直接形成在支撑层上，或者可以通过使附着的中间材料的晶片变薄来形成，然后将其缩小到期望的厚度。

83. 发明申请

US20130234157A1 METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS 有权
标题翻译：形成III类氮化物材料的方法和通过这些方法形成的结构
公开(公告)号：US20130234157A1
公开(公告)日：2013-09-12
申请号：US13988996
申请日：2011-11-23
申请人： Chantal Arena , Ronald Thomas Bertram, JR. , Ed Lindow , Subhash Mahajan , Fanyu Meng
发明人： Chantal Arena , Ronald Thomas Bertram, JR. , Ed Lindow , Subhash Mahajan , Fanyu Meng
IPC分类号： H01L21/02 , H01L29/20
CPC分类号： H01L21/02104 , C30B25/02 , C30B29/403 , C30B29/406 , H01L29/2003
摘要： Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.
摘要翻译：本发明的实施方案包括使用卤化物气相外延（HVPE）方法形成III族氮化物半导体结构的方法。所述方法包括在非天然生长衬底的表面上形成连续的III族氮化物成核层，所述连续III族氮化物成核层隐藏非天然生长衬底的上表面。形成连续的III族氮化物成核层可以包括形成III族氮化物层并热处理所述III族氮化物层。方法还可以包括在连续的III族氮化物成核层上形成另外的III族氮化物层。

84. 发明申请

US20130164874A1 METHODS OF FORMING DILUTE NITRIDE MATERIALS FOR USE IN PHOTOACTIVE DEVICES AND RELATED STRUCTURES 有权
标题翻译：形成用于光电器件和相关结构的稀释氮化物材料的方法
公开(公告)号：US20130164874A1
公开(公告)日：2013-06-27
申请号：US13720524
申请日：2012-12-19
申请人： Chantal Arena , Robin Scott , Claudio Canizares
发明人： Chantal Arena , Robin Scott , Claudio Canizares
IPC分类号： H01L31/18 , H01L33/00 , H01L21/36
CPC分类号： H01L31/184 , H01L21/0254 , H01L21/02546 , H01L21/0262 , H01L27/153 , H01L33/0062 , H01L33/0066 , H01L33/08 , H01L33/32
摘要： Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.
摘要翻译：原子层沉积（ALD）或ALD样沉积工艺用于制造稀氮化物III-V半导体材料。可以使工艺气体的第一组合物流入沉积室，并且除了氮和一个或多个III族元素之外的第V族元素可以被吸附在衬底上（原子或分子形式）。之后，可以使工艺气体的第二组合物流入沉积室，并且可以在沉积室中将N和一个或多个III族元素吸附在衬底上。稀释氮化物III-V半导体材料的外延层可以从沉积室中的顺序吸附元件形成在衬底上。

85. 发明授权

US08436363B2 Metallic carrier for layer transfer and methods for forming the same 有权
标题翻译：用于层转移的金属载体及其形成方法
公开(公告)号：US08436363B2
公开(公告)日：2013-05-07
申请号：US13020288
申请日：2011-02-03
申请人： Christiaan J. Werkhoven , Chantal Arena
发明人： Christiaan J. Werkhoven , Chantal Arena
IPC分类号： H01L31/0256
CPC分类号： H01L21/76256 , H01L21/187 , H01L29/02 , H01L33/007 , H01L33/0079 , H01L33/40 , H01L2933/0016
摘要： Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.
摘要翻译：实施例涉及半导体结构及其形成方法。在一些实施例中，所述方法可用于通过在预定深度处在供体结构中形成弱化区以制造半导体衬底，以在附着表面和弱化区之间限定转移层，以及在弱化区和弱化区之间的残留施主结构与附接表面相对的表面。在附着表面上形成金属层，并且在金属层和转移层之间提供欧姆接触，匹配的金属层的热膨胀系数（CTE）与转印层的CTE紧密匹配，并具有足够的刚度为转移层提供结构支持。在弱化区将转移层与供体结构分离，以形成包含转移层金属层的复合衬底。

86. 发明申请

US20130052806A1 DEPOSITION SYSTEMS HAVING ACCESS GATES AT DESIRABLE LOCATIONS, AND RELATED METHODS 审中-公开
标题翻译：在所需位置具有通道门的沉积系统及相关方法
公开(公告)号：US20130052806A1
公开(公告)日：2013-02-28
申请号：US13591718
申请日：2012-08-22
申请人： Ronald Thomas Bertram, JR. , Christiaan J. Werkhoven , Chantal Arena , Ed Lindow
发明人： Ronald Thomas Bertram, JR. , Christiaan J. Werkhoven , Chantal Arena , Ed Lindow
IPC分类号： C23C16/458 , B23P11/00 , H01L21/20
CPC分类号： C30B25/14 , C23C16/303 , C23C16/45504 , C23C16/4557 , C23C16/54 , C30B29/40 , C30B29/406 , H01L21/02538 , H01L21/0254 , H01L21/0262 , Y10T137/0402
摘要： Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber. The systems also include at least one access gate through which a workpiece substrate may be loaded into the reaction chamber and unloaded out from the reaction chamber. The at least one access gate is located remote from the gas injection device. Methods of depositing semiconductor material may be performed using such deposition systems. Methods of fabricating such deposition systems may include coupling an access gate to a reaction chamber at a location remote from a gas injection device.
摘要翻译：沉积系统包括反应室和至少部分地设置在反应室内的基板支撑结构。该系统还包括至少一个气体注入装置和至少一个真空装置，它们一起用于使工艺气体流过反应室。该系统还包括至少一个进入门，工件基底可通过该入口门装载到反应室中并从反应室中卸载。至少一个进入门位于远离气体注入装置的位置。可以使用这种沉积系统进行半导体材料的沉积方法。制造这种沉积系统的方法可以包括在远离气体注入装置的位置处将进入门连接到反应室。

87. 发明授权

US08367520B2 Methods and structures for altering strain in III-nitride materials 有权
标题翻译：改变III族氮化物材料应变的方法和结构
公开(公告)号：US08367520B2
公开(公告)日：2013-02-05
申请号：US12563327
申请日：2009-09-21
申请人： Chantal Arena
发明人： Chantal Arena
IPC分类号： H01L29/20 , H01L21/18
CPC分类号： H01L21/02639 , H01L21/02521 , H01L21/0254 , H01L21/0265 , H01L21/187
摘要： Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain.
摘要翻译：公开了用于制造具有改进特性的半导体材料，衬底和器件的方法和结构。用于形成减小的应变结构的结构和方法包括在支撑结构表面和应变半导体层之间形成界面。选择性地蚀刻支撑结构以形成具有降低的应变水平的多个半导体岛。

88. 发明授权

US08323407B2 Gallium trichloride injection scheme 有权
标题翻译：三氯化镓注射方案
公开(公告)号：US08323407B2
公开(公告)日：2012-12-04
申请号：US13288396
申请日：2011-11-03
申请人： Chantal Arena , Christiaan Werkhoven
发明人： Chantal Arena , Christiaan Werkhoven
IPC分类号： C30B25/10 , C30B25/14 , C01B21/06 , B01F3/02 , C23C16/08 , C23C16/28 , C23C16/34 , C23C16/448 , C23C16/455 , C01B21/072 , C23C16/452
CPC分类号： C30B25/10 , C23C16/303 , C23C16/4411 , C23C16/4412 , C23C16/45504 , C23C16/45593 , C30B25/14 , C30B29/406 , C30B35/00 , H01L21/0254 , H01L21/0262
摘要： The invention relates to a method and system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The method includes reacting an amount of a gaseous Group III precursor having one or more gaseous gallium precursors as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber; and supplying sufficient energy to the gaseous gallium precursor(s) prior to their reacting so that substantially all such precursors are in their monomer forms. The system includes sources of the reactants, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their component monomers.
摘要翻译：本发明涉及用于外延沉积包含镓的III-V族III族半导体材料的方法和系统。该方法包括使一定量的具有一种或多种气态镓前体的气态III族前体作为一种反应物与一定量的气态V族组分作为反应室中的另一反应物反应; 并在其反应之前向气态镓前体提供足够的能量，使得基本上所有这些前体都是其单体形式。该系统包括反应物的源，其中反应物结合以沉积III-V族半导体材料的反应室，以及一个或多个加热结构，用于在使温度反应至基本上分解所有二聚体，三聚体之前加热气态III族前体或这些前体的其它分子变体转化成它们的组分单体。

89. 发明授权

US08178427B2 Epitaxial methods for reducing surface dislocation density in semiconductor materials 失效
标题翻译：降低半导体材料表面位错密度的外延方法
公开(公告)号：US08178427B2
公开(公告)日：2012-05-15
申请号：US12721461
申请日：2010-03-10
申请人： Chantal Arena , Laurent Clavelier , Marc Rabarot
发明人： Chantal Arena , Laurent Clavelier , Marc Rabarot
IPC分类号： H01L21/20
CPC分类号： H01L29/2003 , H01L21/0242 , H01L21/0243 , H01L21/02458 , H01L21/0254 , H01L21/02639
摘要： The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
摘要翻译：本发明提供了用于减少半导体层的表面位错的方法和结构，并且可以在半导体结构和包含III族氮化物材料的层的外延生长期间使用。实施例涉及形成多个位错坑塞，以防止位错从材料的下层扩散到随后的材料半导体层中。

90. 发明授权

US08154022B2 Process for fabricating a structure for epitaxy without an exclusion zone 有权
标题翻译：用于制造没有排除区的外延结构的方法
公开(公告)号：US08154022B2
公开(公告)日：2012-04-10
申请号：US12912306
申请日：2010-10-26
申请人： Chantal Arena , Fabrice Letertre
发明人： Chantal Arena , Fabrice Letertre
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , Y10T117/10 , Y10T156/1044
摘要： A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
摘要翻译：一种用于制造用于外延的复合结构的方法，包括在支撑衬底上的半导体材料的至少一个结晶生长种子层，所述支撑衬底和所述晶体生长种子层在其结合面的周围具有倒角或边缘圆形区域。该方法包括将结晶生长种子层直接晶片结合到载体基底上的至少一个步骤和至少一个使结晶生长种子层变薄的步骤。在变薄之后，结晶生长种子层具有与其初始直径相同的直径。

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