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81. 发明申请

US20120210073A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120210073A1
公开(公告)日：2012-08-16
申请号：US13025706
申请日：2011-02-11
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus, method and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的装置，方法和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

82. 发明申请

US20120185672A1 LOCAL-ONLY SYNCHRONIZING OPERATIONS 审中-公开
标题翻译：本地同步操作
公开(公告)号：US20120185672A1
公开(公告)日：2012-07-19
申请号：US13008498
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/526 , G06F12/0815 , G06F2209/521
摘要： Performing a series of successive synchronizing operations by a core on data shared by a plurality of cores may include a first core indicating an upcoming synchronizing operation on shared data. A second memory layer stores the shared data and tracks the first core's ownership of the shared data. The second memory layer is shared via coherency operations among the first core and one or more second cores. The first core may perform one or more synchronization operations on the shared data without requiring interaction from the second memory layer.
摘要翻译：通过核心对由多个核心共享的数据执行一系列连续同步操作可以包括指示即将到来的对共享数据的同步操作的第一核心。第二存储器层存储共享数据并跟踪第一核心对共享数据的所有权。通过第一核心和一个或多个第二核心之间的一致性操作来共享第二存储器层。第一核可以对共享数据执行一个或多个同步操作，而不需要来自第二存储器层的交互。

83. 发明申请

US20110173357A1 ARBITRATION IN CROSSBAR INTERCONNECT FOR LOW LATENCY 失效
标题翻译：低边界交叉连接中的仲裁
公开(公告)号：US20110173357A1
公开(公告)日：2011-07-14
申请号：US12684287
申请日：2010-01-08
申请人： Martin Ohmacht , Krishnan Sugavanam
发明人： Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F13/40 , G06F13/368 , G06F13/37
CPC分类号： G06F13/1657
摘要： A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.
摘要翻译：一种用于减少通过交叉开关传送的信号的等待时间的系统和方法和计算机程序产品，所述方法包括在与从属设备相关联的从属仲裁逻辑设备处使用来自一个或多个主设备的访问请求的两个或多个优先权向量信号在每个时钟周期中循环使用，用于选择一个请求主设备，并更新每个时钟周期使用的各个优先级向量信号。类似地，从一个或多个从设备请求访问的每个主机可以具有两个或更多个优先级向量，并且可以在每个时钟周期之间循环，以进一步减少延迟并通过交叉开关提高吞吐量性能。

84. 发明申请

US20110119469A1 BALANCING WORKLOAD IN A MULTIPROCESSOR SYSTEM RESPONSIVE TO PROGRAMMABLE ADJUSTMENTS IN A SYNCRONIZATION INSTRUCTION 审中-公开
标题翻译：在同步指令中对可编程调整负责的多处理器系统中的平衡工作负荷
公开(公告)号：US20110119469A1
公开(公告)日：2011-05-19
申请号：US12796389
申请日：2010-06-08
申请人： Martin Ohmacht
发明人： Martin Ohmacht
IPC分类号： G06F9/38
CPC分类号： G06F3/0604 , G06F3/0655 , G06F3/0671 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834 , G06F9/522 , G06F13/1689 , G06F2003/0697 , G11C7/22
摘要： In a multiprocessor system with threads running in parallel, workload balancing is facilitated by recognizing a plurality of levels of sub-tasks of a memory synchronization instruction and selectively choosing for at least one thread to do less than all of levels of these sub-tasks in response to the memory synchronization instruction. Which thread waits to synchronize can be impacted by this choice. The programmer can cause a thread expected to be a bottleneck to wait less than other threads. Where one thread is a producer and another thread is a consumer, types of memory synchronization can be adapted to these roles.
摘要翻译：在具有并行运行的线程的多处理器系统中，通过识别存储器同步指令的多个级别的子任务并且选择性地选择至少一个线程来执行少于这些子任务的所有级别来促进工作负载平衡响应内存同步指令。哪个线程等待同步可以受到这种选择的影响。程序员可能会导致一个预期是一个瓶颈的线程等待其他线程的等待。哪一个线程是生产者，另一个线程是消费者，内存同步类型可以适应这些角色。

85. 发明授权

US08868975B2 Testing and operating a multiprocessor chip with processor redundancy 有权
标题翻译：测试和操作具有处理器冗余的多处理器芯片
公开(公告)号：US08868975B2
公开(公告)日：2014-10-21
申请号：US13196459
申请日：2011-08-02
申请人： Ralph E. Bellofatto , Steven M. Douskey , Rudolf A. Haring , Moyra K. McManus , Martin Ohmacht , Dietmar Schmunkamp , Krishnan Sugavanam , Bryan J. Weatherford
发明人： Ralph E. Bellofatto , Steven M. Douskey , Rudolf A. Haring , Moyra K. McManus , Martin Ohmacht , Dietmar Schmunkamp , Krishnan Sugavanam , Bryan J. Weatherford
IPC分类号： G06F11/00 , G06F11/22 , G06F11/20
CPC分类号： G06F11/2242 , G06F11/202
摘要： A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
摘要翻译：一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。片上逻辑根据所选的物理到逻辑映射配置处理器内核。

86. 发明授权

US08533399B2 Cache directory look-up re-use as conflict check mechanism for speculative memory requests 有权
标题翻译：缓存目录查找重新用作推测内存请求的冲突检查机制
公开(公告)号：US08533399B2
公开(公告)日：2013-09-10
申请号：US12984252
申请日：2011-01-04
申请人： Martin Ohmacht
发明人： Martin Ohmacht
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/3834 , Y02D10/13
摘要： In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.
摘要翻译：在高速缓冲存储器中，能够通过保存高速缓存目录查找的结果来实现能量和其他效率，以便顺序访问相同的存储器地址。在缓存是多处理器系统中用于推测执行的一致性点的情况下，使用目录查找作为冲突检测点，这种保存变得特别有利。

87. 发明申请

US20120324142A1 LIST BASED PREFETCH 有权
标题翻译：以列表为前提
公开(公告)号：US20120324142A1
公开(公告)日：2012-12-20
申请号：US13593838
申请日：2012-08-24
申请人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
摘要翻译：列表预取引擎提高并行计算系统的性能。列表预取引擎接收当前高速缓存未命中地址。列表预取引擎评估当前缓存未命中地址是否有效。如果当前高速缓存未命中地址有效，则列表预取引擎将比较当前高速缓存未命中地址和列表地址。列表地址表示列表中的地址。列表描述了先前高速缓存未命中地址的任意序列。如果当前缓存未命中地址和列表地址之间存在匹配，则预取引擎将根据列表预取数据。

88. 发明授权

US08312193B2 Eager protocol on a cache pipeline dataflow 有权
标题翻译：缓存流水线数据流上的Eager协议
公开(公告)号：US08312193B2
公开(公告)日：2012-11-13
申请号：US12684630
申请日：2010-01-08
申请人： Martin Ohmacht , Krishnan Sugavanam
发明人： Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F13/372
CPC分类号： G06F13/4022
摘要： A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate with the slave device, and the master device sends data associated with the request to communicate at least after the period of cycles has passed since the master device sent the request to communicate to the switch without waiting to receive an acknowledgment from the switch that the master device can communicate with the slave device.
摘要翻译：主设备向交换机发送与从设备通信的请求。主设备等待切换所需的周期周期以决定主设备是否可以与从设备进行通信，并且主设备至少在从主设备经过周期之后至少发送与该请求相关联的数据发送与交换机进行通信的请求，而不用等待从交换机接收到主设备可以与从设备通信的确认。

89. 发明申请

US20110219187A1 CACHE DIRECTORY LOOKUP READER SET ENCODING FOR PARTIAL CACHE LINE SPECULATION SUPPORT 有权
标题翻译： CACHE DIRECTORY LOOKUP READER SET ENCODING FOR CLASS CACHE LINE SPECTRATION SUPPORT
公开(公告)号：US20110219187A1
公开(公告)日：2011-09-08
申请号：US13008602
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht
发明人： Alan Gara , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, with conflict checking implemented in a directory lookup of a shared cache memory, a reader set encoding permits dynamic recordation of read accesses. The reader set encoding includes an indication of a portion of a line read, for instance by indicating boundaries of read accesses. Different encodings may apply to different types of speculative execution.
摘要翻译：在多处理器系统中，通过在共享高速缓冲存储器的目录查找中实现冲突检查，读取器集合编码允许读取访问的动态记录。读取器组编码包括例如通过指示读取访问的边界来读取行的一部分的指示。不同的编码可能适用于不同类型的投机执行。

90. 发明申请

US20110202731A1 CACHE WITHIN A CACHE 有权
标题翻译： CACHE内的缓存
公开(公告)号：US20110202731A1
公开(公告)日：2011-08-18
申请号：US12984252
申请日：2011-01-04
申请人： Martin Ohmacht
发明人： Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/3834 , Y02D10/13
摘要： In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of coherence for speculative execution in a multiprocessor system, with directory lookups serving as the point of conflict detection, such saving becomes particularly advantageous.
摘要翻译：在高速缓冲存储器中，能够通过保存高速缓存目录查找的结果来实现能量和其他效率，以便顺序访问相同的存储器地址。在缓存是多处理器系统中用于推测执行的一致性点的情况下，使用目录查找作为冲突检测点，这种保存变得特别有利。

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