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    • 85. 发明授权
    • Burner for decomposing nonflammable materials
    • 用于分解不燃材料的燃烧器
    • US06755645B2
    • 2004-06-29
    • US10336040
    • 2003-01-03
    • Atsuko SeoWataru FujisakiToshiji AmanoKenichi NakamuraKenichi SugiharaPark Byoung-SupJin Bingzhe
    • Atsuko SeoWataru FujisakiToshiji AmanoKenichi NakamuraKenichi SugiharaPark Byoung-SupJin Bingzhe
    • F23D1400
    • F23G7/065F23G2209/142
    • There is provided a burner for decomposing nonflammable materials, which is simple in structure and capable of thermally decomposing even a material which is relatively high in thermal decomposition temperature such as CF4 at as high efficiency as 99% or more. This burner comprises a nonflammable material-containing gas-introducing nozzle (40) which is disposed at one end of a cylindrical body (2) so as to enable the nonflammable material-containing gas to be injected around the center along the direction to the central axis (L) of the cylindrical body (2), and a plurality of oxidizing agent/fuel blow-off nozzles are disposed in a manner that these nozzles are positioned on and along circular lines which are coaxial with the central axis (L) of the cylindrical body (2). These blow-off nozzles (50) are inclined in such a degree as to enable flames (f) ejected therefrom to converge onto approximately the same point on the central axis of the cylindrical body (2).
    • 提供了一种用于分解不燃材料的燃烧器,其结构简单,并且即使是热分解温度较高的材料(如CF4)也能以99%以上的高效率进行热分解。 该燃烧器包括设置在圆筒体(2)的一端的不易燃材料的气体导入喷嘴(40),以使得不易燃的含材料气体能够沿着中心方向注入中心 圆柱体(2)的轴线(L),并且多个氧化剂/燃料吹出喷嘴以这样的方式设置,使得这些喷嘴位于沿着与中心轴线(L)同轴的圆形线 圆柱体(2)。 这些吹出喷嘴(50)的倾斜程度使得能够从其喷射的火焰(f)会聚到圆筒体(2)的中心轴上的大致相同的点上。
    • 88. 发明授权
    • Semiconductor memory device
    • 动态型半导体存储器件
    • US06262922B1
    • 2001-07-17
    • US09542544
    • 2000-04-03
    • Kenichi NakamuraTakashi ItoYutaka YoshitaniTomokazu Kawase
    • Kenichi NakamuraTakashi ItoYutaka YoshitaniTomokazu Kawase
    • G11C700
    • G11C7/1057G11C7/1048G11C7/1051
    • There is provided a DRAM capable of carrying out rapid data readout. The DRAM includes a memory cell array 1; a row decoder 3 for selectively driving word lines; a bit line sense amplifier 2 for controlling data, which are read out to a plurality of bit lines by driving the word lines, by a first sense amplifier activating signal to detect and amplify the data; a column selecting gate 5, which is driven by a column selecting signal generated behind the first sense amplifier activating signal, for connecting the selected bit line to a corresponding data line; and a data line sense amplifier, which is connected to the data line and which is controlled by a second sense amplifier activating signal generated behind the column selecting signal, the data line sense amplifier being associated with the bit line sense amplifier for detecting and amplifying data transmitted to the data line by the data selecting gate 5.
    • 提供了能够执行快速数据读出的DRAM。 DRAM包括存储单元阵列1; 用于选择性地驱动字线的行解码器3; 位线读出放大器2,用于通过第一读出放大器激活信号控制通过驱动字线而被读出到多个位线的数据,以检测和放大数据; 列选择门5,其由在第一读出放大器激活信号之后产生的列选择信号驱动,用于将所选择的位线连接到相应的数据线; 以及数据线读出放大器,其连接到数据线并且由在列选择信号之后产生的第二读出放大器激活信号控制,数据线读出放大器与位线读出放大器相关联,用于检测和放大数据 由数据选择门5发送到数据线。
    • 90. 发明授权
    • Semiconductor device
    • 半导体器件
    • US5942784A
    • 1999-08-24
    • US891558
    • 1997-07-11
    • Takayuki HarimaKenichi NakamuraMitsugi Ogura
    • Takayuki HarimaKenichi NakamuraMitsugi Ogura
    • H01L21/8238H01L27/08H01L27/092H03K19/094H01L29/76H01L29/94
    • H01L27/0921
    • A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.
    • 公开了一种实现高速访问并且防止由多个电源对闩锁进行任何功率输入序列的半导体器件。 在芯片电压VDD较早输入的地方,N阱偏置电路9和P阱偏置电路10被激活,N型阱12和P型阱13分别被偏置。 之后,虽然输入了接口电压VDDQ,但是不产生闭锁。 另一方面,在接口电压VDDQ较早地输入端子8的情况下,N阱偏压电路9和P阱偏置电路10通过旁路电路15被激活,N型阱12和P- 类型井13有偏差。 因此,尽管在此之后输入芯片电压VDD,但是不产生闩锁。