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1. 发明授权

US06262922B1 Semiconductor memory device 失效
标题翻译：动态型半导体存储器件
公开(公告)号：US06262922B1
公开(公告)日：2001-07-17
申请号：US09542544
申请日：2000-04-03
申请人： Kenichi Nakamura , Takashi Ito , Yutaka Yoshitani , Tomokazu Kawase
发明人： Kenichi Nakamura , Takashi Ito , Yutaka Yoshitani , Tomokazu Kawase
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1048 , G11C7/1051
摘要： There is provided a DRAM capable of carrying out rapid data readout. The DRAM includes a memory cell array 1; a row decoder 3 for selectively driving word lines; a bit line sense amplifier 2 for controlling data, which are read out to a plurality of bit lines by driving the word lines, by a first sense amplifier activating signal to detect and amplify the data; a column selecting gate 5, which is driven by a column selecting signal generated behind the first sense amplifier activating signal, for connecting the selected bit line to a corresponding data line; and a data line sense amplifier, which is connected to the data line and which is controlled by a second sense amplifier activating signal generated behind the column selecting signal, the data line sense amplifier being associated with the bit line sense amplifier for detecting and amplifying data transmitted to the data line by the data selecting gate 5.
摘要翻译：提供了能够执行快速数据读出的DRAM。 DRAM包括存储单元阵列1; 用于选择性地驱动字线的行解码器3; 位线读出放大器2，用于通过第一读出放大器激活信号控制通过驱动字线而被读出到多个位线的数据，以检测和放大数据; 列选择门5，其由在第一读出放大器激活信号之后产生的列选择信号驱动，用于将所选择的位线连接到相应的数据线; 以及数据线读出放大器，其连接到数据线并且由在列选择信号之后产生的第二读出放大器激活信号控制，数据线读出放大器与位线读出放大器相关联，用于检测和放大数据由数据选择门5发送到数据线。

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