专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07072205B2 Floating-body DRAM with two-phase write 失效
标题翻译：具有两相写入的浮体DRAM
公开(公告)号：US07072205B2
公开(公告)日：2006-07-04
申请号：US10716755
申请日：2003-11-19
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： G11C11/4094 , G11C11/404 , G11C11/4076 , G11C11/4085
摘要： A row of floating-body single transistor memory cells is written to in two phases.
摘要翻译：一行浮体单晶体管存储单元分两个阶段写入。

82. 发明授权

US07002842B2 Floating-body dynamic random access memory with purge line 失效
公开(公告)号：US07002842B2
公开(公告)日：2006-02-21
申请号：US10721184
申请日：2003-11-26
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

83. 发明授权

US07001811B2 Method for making memory cell without halo implant 失效
标题翻译：制造无光晕植入记忆细胞的方法
公开(公告)号：US07001811B2
公开(公告)日：2006-02-21
申请号：US10750566
申请日：2003-12-31
申请人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： H01L21/336
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

84. 发明授权

US06801465B2 Apparatus and method for a memory storage cell leakage cancellation scheme 有权
标题翻译：用于存储器存储单元泄漏消除方案的装置和方法
公开(公告)号：US06801465B2
公开(公告)日：2004-10-05
申请号：US10461293
申请日：2003-06-13
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.
摘要翻译：描述了具有耦合在第一位线和第二位线之间的多个存储单元的装置。该装置还具有第一晶体管，其对第一位线进行预充电，并为多个存储单元中的任何一个提供从第一位线提取的一个或多个泄漏电流的第一电流。该装置还具有第二晶体管，其对第二位线进行预充电并且为多个存储单元中的任一个提供从第二位线提取的一个或多个泄漏电流的第二电流供应。

85. 发明授权

US06653866B2 Domino logic with output predischarge 有权
公开(公告)号：US06653866B2
公开(公告)日：2003-11-25
申请号：US10277009
申请日：2002-10-21
申请人： Siva G. Narendra , Yibin Ye , Vivek K. De
发明人： Siva G. Narendra , Yibin Ye , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/01728
摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

86. 发明授权

US06608786B2 Apparatus and method for a memory storage cell leakage cancellation scheme 有权
公开(公告)号：US06608786B2
公开(公告)日：2003-08-19
申请号：US09823575
申请日：2001-03-30
申请人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Fatih Hamzaoglu , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.

87. 发明授权

US06316960B2 Domino logic circuit and method 失效
标题翻译：多米诺逻辑电路和方法
公开(公告)号：US06316960B2
公开(公告)日：2001-11-13
申请号：US09286914
申请日：1999-04-06
申请人： Yibin Ye
发明人： Yibin Ye
IPC分类号： H03K19096
CPC分类号： H03K19/096
摘要： A domino logic circuit includes input connections to receive a clock signal and an input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal. The n-channel pull-up transistor has a low threshold voltage. The dynamic stage can include an n-channel pull-down transistor which has a gate connection coupled to receive the clock signal. First and second inverter circuits can also be provided to latch a voltage on a drain of the pull-down transistor. Static logic circuits coupled to the dynamic stage have skewed rise and fall times to increase the propagation time of the domino circuit.
摘要翻译：多米诺逻辑电路包括用于接收时钟信号和输入数据信号的输入连接。在一个实施例中，多米诺逻辑电路包括动态级，其包括至少一个n沟道上拉晶体管，其具有耦合以接收输入数据信号的栅极。 n沟道上拉晶体管具有低阈值电压。动态级可以包括n沟道下拉晶体管，其具有耦合以接收时钟信号的栅极连接。还可以提供第一和第二反相器电路以锁存下拉晶体管的漏极上的电压。耦合到动态级的静态逻辑电路具有偏斜的上升和下降时间，以增加多米诺骨电路的传播时间。

88. 发明授权

US06275071B1 Domino logic circuit and method 有权
标题翻译：多米诺逻辑电路和方法
公开(公告)号：US06275071B1
公开(公告)日：2001-08-14
申请号：US09474533
申请日：1999-12-29
申请人： Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit includes input connections to receive a clock signal and at least one input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising precharge circuitry, and a static stage that comprises discharge circuitry. In another embodiment, the domino logic circuit includes a dynamic stage comprising discharge circuitry, and a static stage that comprises precharge circuitry. Different configurations and transistor types have also been described. The circuitry can provide improved speed performance, or increase noise immunity.
摘要翻译：多米诺逻辑电路包括用于接收时钟信号和至少一个输入数据信号的输入连接。在一个实施例中，多米诺逻辑电路包括包括预充电电路的动态级和包括放电电路的静态级。在另一个实施例中，多米诺骨牌逻辑电路包括包括放电电路的动态级和包括预充电电路的静态级。还描述了不同的配置和晶体管类型。该电路可以提供改进的速度性能，或提高抗噪声能力。

89. 发明授权

US08746726B2 Trailer coupler 有权
标题翻译：拖车联轴器
公开(公告)号：US08746726B2
公开(公告)日：2014-06-10
申请号：US13485785
申请日：2012-05-31
申请人： Yibin Ye
发明人： Yibin Ye
IPC分类号： B60D1/06
CPC分类号： B60D1/06 , B60D1/065 , Y10T29/49826
摘要： A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.
摘要翻译：拖车联轴器可以设置有用于搭接球的开口和插座，以及用于锁定联接器并搭接在一起的内部通道中的夹紧杆。内部通道可以水平延伸并且定位在开口的上方并且在插座下方。通道可以包括邻近第二端的横向对置的孔，夹紧杆的一端可以延伸。夹紧杆的端部可以包括具有敞开通道的支架，以配合在耦合器主体上的凸缘上。联接器可以通过将夹紧杆的第一端插入横向相对的孔中来组装，并且将夹持杆的第一端移动到联接器主体通道中，同时将支架安装在夹紧杆的开放通道上方的凸缘上。

90. 发明授权

US07397395B2 Representative majority voter for bus invert coding 有权
标题翻译：代表大多数选民为总线反转编码
公开(公告)号：US07397395B2
公开(公告)日：2008-07-08
申请号：US11059174
申请日：2005-02-16
申请人： James W Tschanz , Mircea R. Stan , Muhammad M Khellah , Yibin Ye , Vivek K De
发明人： James W Tschanz , Mircea R. Stan , Muhammad M Khellah , Yibin Ye , Vivek K De
IPC分类号： H03M7/00
CPC分类号： G06F13/4213 , H03K19/23 , H03M5/145 , Y02D10/14 , Y02D10/151
摘要： In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
摘要翻译：一般来说，在一个方面，本公开描述了一种包括代表性的多数选民门来分析多个位的位转换的装置。分组的分类分析。代表大多数选民门根据分析产生反转信号。该装置进一步包括条件反相器将反相信号应用于多个位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式