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    • 81. 发明专利
    • Semiconductor device
    • 半导体器件
    • JPS5735374A
    • 1982-02-25
    • JP11195980
    • 1980-08-11
    • Mitsubishi Electric Corp
    • OOHAYASHI YOSHIKAZUDENDA MASAHIKOSATOU SHINICHIKINOSHITA SHIGEJITSUBOUCHI NATSUO
    • H03F1/52H01L27/02H01L27/06H01L29/78H02H7/20H03F1/42
    • H01L27/0255
    • PURPOSE:To lower the reverse voltage resisting capability of a protective diode by a method wherein impurity concentration is kept low in a substrate surface. CONSTITUTION:A highly doped P type semiconductor substrate 1 is covered with an epitaxially grown single crystal semiconductor layer 2 that possesses the same type of conductivity as the substrate 1 but is sufficiently lower as regards impurity concentration than in the substrate 1. The surface of the single crystal semiconductor layer 2 is then subjected to such a heat treatment process as ion injection or diffusion which results in the formation of a semiconductor domain 3 conductive feature whereof is different from the substrate 1 thanks to the introduction of highly concentrated impurities with a different conductive feature. The domain 3 extends to the highly doped substrate 1. The domain 3 thus has two junctions: a P-N type junction wherein the bottom of the domain 3 meets the substrate 1 at a junction 4 and the other wherein the side of the domain 3 meets the semiconductor 2 at a junction 5.
    • 目的:通过在衬底表面中保持低浓度的方法降低保护二极管的反向耐压能力。 构成:高掺杂P型半导体衬底1被外延生长的单晶半导体层2覆盖,该外延生长单晶半导体层2具有与衬底1相同的导电性,但是相对于衬底1而言,杂质浓度足够低。 然后将单晶半导体层2进行离子注入或扩散的这种热处理工艺,由于引入了具有不同导电性的高浓度杂质,导致半导体区域3的导电特征不同于衬底1 特征。 结构域3延伸到高度掺杂的衬底1.畴3因此具有两个结:PN型结,其中结构域3的底部在结4处与衬底1相遇,另一个结合域3的一侧与 半导体2在5号接头处。
    • 82. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS571252A
    • 1982-01-06
    • JP7520680
    • 1980-06-03
    • MITSUBISHI ELECTRIC CORP
    • DENDA MASAHIKOSATOU SHINICHITSUBOUCHI NATSUOKINOSHITA SHIGEJIOOHAYASHI YOSHIKAZU
    • H01L27/10H01L21/8242H01L27/108
    • PURPOSE:To obtain a memory unit being strong to alpha rays by a method wherein in a semiconductor substrate, specific resistance of the substrate is made t differ between a capacitor part and a transistor part. CONSTITUTION:Specific resistance of the P type Si substrate 6 having crystal orientation of is made as 1-0.01OMEGAcm. Specific resistance of an ion implanting part 8 is enhanced by selective ion implantation of an N type impurity having a diffusion coefficient being the same grade with the P type impurity. Then a P type layer 7 having specific resistance of about 10OMEGAcm being the same grade with the layer 8 is formed by vapor growth. When heat treatment is performed in succession, the layer on the inside region 6a of the substrate is held as a P type layer, but on the layer 8, because impurities of P type and N type are compensated, specific resistance of the substrate is held at high. Because the life of electrons and holes in the region 6a is short, almost no electron reaches the capacitor part, therefore almost no effect is applied by electrons generated in the P layer 6a part. Moreover because the layer 8 under a gate electrode 3 of the transistor has high specific resistance, almost no effect is applied to characteristic of the transistor. Accordingly the memory being strong to alpha rays can be obtained without deterioration of characteristic.
    • 87. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPS5666063A
    • 1981-06-04
    • JP14178279
    • 1979-10-31
    • MITSUBISHI ELECTRIC CORP
    • DENDA MASAHIKOSATOU SHINICHITSUBOUCHI NATSUO
    • H01L27/10H01L21/8234H01L21/8242H01L27/06H01L27/088H01L27/108H01L29/78
    • PURPOSE:To prevent the influence of alpha rays irradiating from the outside to a semiconductor device by a method wherein an oxide film is formed corresponding to a capacitor region on the semiconductor substrate, the film is covered with a polycrystalline Si layer of the same conductive type with the substrate, and a polycrystalline Si gate electrode is provided at one side face installing a gate oxide film between them. CONSTITUTION:The SiO2 film 12 is formed corresponding to the capacitor region on the P type Si substrate 11, the exposed upper surface and the side faces are surrounded with the polycrystalline Si film 14 and the same impurity with the substrate 11 is doped therein to impart the conductively. The first gate oxide film 15 is formed covering it, and the first polycrystalline Si film 16 is adhered on it. The gate electrode 18 consisting of the second polycrystalline Si film 17 is provided on its one side face with the entermediary of the second gate oxide film 17, and an N type region 19 is diffusion formed in the substrate to be in contact with the electrode 18 to form a memory cell. By this constitution, even if electrons or holes may be generated by the irradiation of alpha rays from the outside, they can not reach the cell.