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81. 发明授权

US06444373B1 Modification of mask layout data to improve mask fidelity 有权
标题翻译：修改掩模布局数据以提高掩码保真度
公开(公告)号：US06444373B1
公开(公告)日：2002-09-03
申请号：US09596954
申请日：2000-06-16
申请人： Ramkumar Subramanian , Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Ramkumar Subramanian , Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： G03F900
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70441
摘要： The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.
摘要翻译：本发明涉及一种修改掩模布局数据以提高掩模制造的保真度的系统和方法。该系统和方法包括确定掩模布局设计和掩模特征之间的写入差异，并产生尺寸校正。尺寸校正可用于修改掩模布局数据和/或存储在数据库中。

82. 发明授权

US06423479B1 Cleaning carbon contamination on mask using gaseous phase 失效
标题翻译：使用气相清洁面罩上的碳污染
公开(公告)号：US06423479B1
公开(公告)日：2002-07-23
申请号：US09495165
申请日：2000-01-31
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
IPC分类号： G03F726
CPC分类号： G03F1/82
摘要： In one embodiment, the present invention relates to a method of processing a lithography mask, involving the steps of exposing a lithography substrate with actinic radiation through the lithography mask in a chamber; removing the lithography mask from the chamber, wherein the lithography mask contains carbon contaminants; and contacting the lithography mask with sulfur trioxide thereby reducing the carbon contaminants thereon.
摘要翻译：在一个实施例中，本发明涉及一种处理光刻掩模的方法，包括以下步骤：将具有光化辐射的光刻基底通过室中的光刻掩模曝光; 从所述腔室去除所述光刻掩模，其中所述光刻掩模含有碳污染物; 并使光刻掩模与三氧化硫接触，从而减少其上的碳污染物。

83. 发明授权

US06417084B1 T-gate formation using a modified conventional poly process 有权
标题翻译：使用改进的常规聚合方法形成T形栅
公开(公告)号：US06417084B1
公开(公告)日：2002-07-09
申请号：US09620300
申请日：2000-07-20
申请人： Bhanwar Singh , Marina Plat , Ramkumar Subramanian , Christopher F. Lyons
发明人： Bhanwar Singh , Marina Plat , Ramkumar Subramanian , Christopher F. Lyons
IPC分类号： H01L213205
CPC分类号： H01L21/28114 , H01L21/32139
摘要： A method is provided for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer over the polysilicon layer. A gate structure is formed by removing the ARC layer and a portion of the polysilicon layer around a gate region. Spacers are then formed around the gate structure. Undercut regions are formed in the gate structure by performing an isotropic etch to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region.
摘要翻译：提供了一种用于制造T型栅结构的方法。提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层以及多晶硅层上的ARC层。通过在栅极区域周围除去ARC层和多晶硅层的一部分来形成栅极结构。然后在栅极结构周围形成间隔物。通过执行各向同性蚀刻在栅极结构中形成底切区域，以向栅极结构提供基极区域和接触区域。基部区域的宽度小于接触区域。

84. 发明授权

US06371134B1 Ozone cleaning of wafers 有权
公开(公告)号：US06371134B1
公开(公告)日：2002-04-16
申请号：US09495014
申请日：2000-01-31
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Sanjay K. Yedur , Bryan K. Choo
IPC分类号： B08B700
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.

85. 发明授权

US06319802B1 T-gate formation using modified damascene processing with two masks 有权
标题翻译：使用具有两个掩模的改良镶嵌加工的T形栅结构
公开(公告)号：US06319802B1
公开(公告)日：2001-11-20
申请号：US09620145
申请日：2000-07-20
申请人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
发明人： Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh , Marina Plat
IPC分类号： H01L213205
CPC分类号： H01L21/28114
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer and a sacrificial layer over the protection layer. An opening is then formed in the sacrificial layer. A contact material is deposited over the sacrificial layer filling the opening with the contact material and forming a contact layer. Portions of the contact material outside a gate region are then removed. Finally, the sacrificial layer and portions of the protection layer and the gate oxide layer not forming a part of the T-gate structure are removed.
摘要翻译：提供了一种制造T型栅结构的方法。提供了一种具有硅层的结构，该硅层具有栅极氧化物层，栅极氧化物层上的保护层和保护层上的牺牲层。然后在牺牲层中形成开口。接触材料沉积在用接触材料填充开口的牺牲层上并形成接触层。然后去除栅极区域外部的接触材料的部分。最后，除去牺牲层和不形成T栅结构的一部分的保护层和栅极氧化物层的部分。

86. 发明授权

US07604903B1 Mask having sidewall absorbers to enable the printing of finer features in nanoprint lithography (1XMASK) 有权
标题翻译：具有侧壁吸收器的面罩能够在纳米印刷光刻（1XMASK）中印刷更精细的特征，
公开(公告)号：US07604903B1
公开(公告)日：2009-10-20
申请号：US10768515
申请日：2004-01-30
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G03F1/00 , G03F1/14
CPC分类号： G03F1/50
摘要： A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.
摘要翻译：提供掩模以与纳米印刷光刻工艺一起使用，以便于再现生产集成电路所需的小特征。提供了一个半透明衬底以及包括一个或多个垂直侧壁的一个或多个三维特征。吸收材料沉积在一个或多个垂直侧壁上，使得在衬底的上表面的入射方向上的光将被吸收材料吸收，导致阻光特征。一个或多个水平表面形成在三维特征中的一个或多个上，这允许光线离开衬底的下表面而不被吸收材料阻挡。

87. 发明授权

US07449348B1 Feedback control of imprint mask feature profile using scatterometry and spacer etchback 有权
标题翻译：使用散射法和间隔蚀刻蚀刻对印迹掩模特征轮廓的反馈控制
公开(公告)号：US07449348B1
公开(公告)日：2008-11-11
申请号：US10858605
申请日：2004-06-02
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan
IPC分类号： H01L21/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L22/12
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.
摘要翻译：本发明一般涉及光刻系统和方法，更具体地涉及有助于补偿压印掩模上逆行特征轮廓的系统和方法。本发明的一个方面产生反馈信息，其通过使用散射测量系统来检测逆行特征轮廓，以及通过间隔回蚀程序来缓解逆行轮廓，从而有助于控制压印掩模特征轮廓。

88. 发明授权

US07309659B1 Silicon-containing resist to pattern organic low k-dielectrics 有权
标题翻译：含硅抗蚀剂图案有机低k电介质
公开(公告)号：US07309659B1
公开(公告)日：2007-12-18
申请号：US11097029
申请日：2005-04-01
申请人： Ramkumar Subramanian , Calvin T. Gabriel , Bhanwar Singh
发明人： Ramkumar Subramanian , Calvin T. Gabriel , Bhanwar Singh
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/76802 , H01L21/7681 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.
摘要翻译：本公开提供了减轻和/或消除与有机低k电介质去除碳基抗蚀剂有关的问题的方法。所述方法包括在半导体衬底上形成有机低k电介质层，在有机低k电介质层上形成覆盖层，在覆盖层上形成含硅抗蚀剂，图案化含硅抗蚀剂层以暴露部分并且形成图案化氧化硅层，去除有机低k电介质层以形成一个或多个开口，以及去除图案化的氧化硅层。含硅抗蚀剂有利于有机低k电介质层的有效构图，从而提高使用有机低k电介质制造的半导体器件的性能和成本效益。

89. 发明授权

US07221060B1 Composite alignment mark scheme for multi-layers in lithography 有权
标题翻译：光刻多层复合对准标记方案
公开(公告)号：US07221060B1
公开(公告)日：2007-05-22
申请号：US11074602
申请日：2005-03-08
申请人： Bhanwar Singh , Khoi A. Phan , Bharath Rangarajan , Iraj Emami , Ramkumar Subramanian
发明人： Bhanwar Singh , Khoi A. Phan , Bharath Rangarajan , Iraj Emami , Ramkumar Subramanian
IPC分类号： H01L23/544
CPC分类号： G03F7/70625 , G03F7/70633 , G03F9/7076 , Y10S438/975
摘要： Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.
摘要翻译：公开了用于对准多层半导体器件制造工艺和/或利用复合对准标记的系统的多层的系统和/或方法。提供组件以形成复合对准标记，使得复合对准标记的第一部分与晶片的层相关联，并且复合对准标记的第二部分与晶片的不同层相关联。使用对准部件将待图案化的层的掩模版对准到复合对准标记。

90. 发明授权

US07109046B1 Surface oxide tabulation and photo process control and cost savings 失效
标题翻译：表面氧化物制图和照相工艺控制和成本节约
公开(公告)号：US07109046B1
公开(公告)日：2006-09-19
申请号：US10768514
申请日：2004-01-30
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： H01L21/00
CPC分类号： H01L22/12
摘要： The present invention relates generally to semiconductor processing, and more particularly to methods and systems for reducing costs of wafer production by analyzing key aspects of wafer status to determine whether to initiate corrective measures to salvage a wafer at an early stage and before substantial costs are incurred in fabricating a defective wafer. One aspect of the present invention provides for growing an oxide layer on a wafer upon a determination that an oxide layer on the wafer surface is absent or is present but inadequate. Another aspect of the present invention provides for a determination of whether to apply preemptory corrective treatment(s) to a wafer surface based on the presence and/or magnitude of nitrogen signatures in an extant oxide surface layer, which can indicate that an undesirable defect known as “footing” will occur during a post-exposure delay period. Thus, the invention advantageously reduces production costs by facilitating a most correct decision to mitigate the source(s) of potential defects at an early stage and, thus, before substantial costs are incurred in production of the wafer.
摘要翻译：本发明一般涉及半导体处理，更具体地说，涉及通过分析晶片状态的关键方面来降低晶片生产成本的方法和系统，以确定是否启动在早期阶段挽救晶片的纠正措施以及在大量成本产生之前在制造缺陷晶片时。本发明的一个方面提供了在确定晶片表面上的氧化物层不存在或存在但不足的情况下，在晶片上生长氧化物层。本发明的另一方面提供了根据现有氧化物表面层中氮标记的存在和/或大小来确定是否对晶片表面施加抢占式校正处理，其可以指示不期望的缺陷已知因为在曝光后延迟期间将发生“立足”。因此，本发明有利地通过促进最正确的决定来降低生产成本，以在早期阶段减轻潜在缺陷的来源，并且因此在生产晶片之前花费大量成本之前。

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