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81. 发明授权

US06744087B2 Non-volatile memory using ferroelectric gate field-effect transistors 有权
标题翻译：使用铁电栅极场效应晶体管的非易失性存储器
公开(公告)号：US06744087B2
公开(公告)日：2004-06-01
申请号：US10256881
申请日：2002-09-27
申请人： James A. Misewich , William Robert Reohr , Alejandro Gabriel Schrott , Li-Kong Wang
发明人： James A. Misewich , William Robert Reohr , Alejandro Gabriel Schrott , Li-Kong Wang
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L27/11507 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391
摘要： A vertical ferroelectric gate field-effect transistor (FeGFET) device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes. A non-volatile memory array can be formed comprising a plurality of FeGFET devices.
摘要翻译：垂直铁电栅极场效应晶体管（FeGFET）器件包括形成在衬底的上表面上的衬底和第一漏极/源极。在第一漏/源电极的上表面上形成导电沟道区，并与第一漏/源电极电接触。 FeGFET器件还包括形成在通道区域的至少一个侧壁上的铁电栅极区域，与铁电栅极区域电接触的至少一个栅极电极和形成在沟道区域的上表面上的第二漏极/源极电极，以及电接触通道区域。铁电栅极区域响应于施加在栅极电极和第一和第二漏极/源极电极中的至少一个之间的电位而选择性地极化。可以形成包括多个FeGFET装置的非易失性存储器阵列。

82. 发明授权

US06624526B2 Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating 有权
$Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating$
标题翻译：含有难熔金属 - 硅 - 氮电阻元件的紧凑SRAM单元及其制造方法
公开(公告)号：US06624526B2
公开(公告)日：2003-09-23
申请号：US09872325
申请日：2001-06-01
申请人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
发明人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.
摘要翻译：描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

83. 发明授权

US06198677B1 Boosted sensing ground circuit 失效
标题翻译：增强的感测接地电路
公开(公告)号：US06198677B1
公开(公告)日：2001-03-06
申请号：US09221629
申请日：1998-12-29
申请人： Louis Hsu , Li-Kong Wang
发明人： Louis Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C7/06
摘要： A new noise control circuit which connects the sense ground node to ground in two specific period of times so that the NSA bouncing is minimized. Preferably these two periods are at the beginning of setting the n-type latch and when the data is transferring and CSL is switching. A pulse of NSET and together with whole CSLEN signal are used to activate the noise control circuit. The noise control circuit can also include a n-FET diode with its gate connected to the source and its drain tied to the Vbleq power supply. It is more preferable to use a low threshold voltage of n-FET device with Vt at 0.55 volts to form the clamp diode.
摘要翻译：一种新的噪声控制电路，其在两个特定时间段内将感测接地节点连接到地面，使得NSA弹跳最小化。优选地，这两个周期在设置n型锁存器的开始处以及当数据正在传送和CSL正在切换时。使用NSET的脉冲和整个CSLEN信号来激活噪声控制电路。噪声控制电路还可以包括n-FET二极管，其栅极连接到源极，其漏极连接到Vbleq电源。更优选使用0.5V的Vt的n-FET器件的低阈值电压来形成钳位二极管。

84. 发明授权

US4435895A Process for forming complementary integrated circuit devices 失效
标题翻译：用于形成互补集成电路器件的工艺
公开(公告)号：US4435895A
公开(公告)日：1984-03-13
申请号：US365396
申请日：1982-04-05
申请人： Louis C. Parrillo , George W. Reutlinger , Li-Kong Wang
发明人： Louis C. Parrillo , George W. Reutlinger , Li-Kong Wang
IPC分类号： H01L29/78 , H01L21/265 , H01L21/266 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/06 , H01L21/22
CPC分类号： H01L21/266 , H01L21/26513 , H01L21/823878 , H01L29/0638 , H01L27/0928
摘要： A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.
摘要翻译：一种用于在互补晶体管集成电路器件中形成通孔的方法，其仅涉及一个额外的掩模步骤，但是允许密闭地控制在阻塞中的掺杂。该方法有利地从用于形成CMOS集成电路器件的双槽结构开始使用。

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