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81. 发明授权

US06794721B2 Integration system via metal oxide conversion 有权
公开(公告)号：US06794721B2
公开(公告)日：2004-09-21
申请号：US10328650
申请日：2002-12-23
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L2976
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28518 , H01L21/28568 , H01L21/3003 , H01L21/76823 , H01L21/76895 , H01L29/517 , H01L29/7833
摘要： A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.

82. 发明授权

US06720595B2 Three-dimensional island pixel photo-sensor 有权
标题翻译：三维岛像素光电传感器
公开(公告)号：US06720595B2
公开(公告)日：2004-04-13
申请号：US09922077
申请日：2001-08-06
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L31062
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
摘要翻译：公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。利用本发明，侧壁垂直于接收入射光的光电二极管的表面。感光侧壁包括当用光照射时引起电子转移的结区域。侧壁包围围绕每个岛芯的四个垂直侧壁。逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

83. 发明授权

US06563160B2 High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits 失效
标题翻译：形成DRAM的组件的高介电常数材料，例如用于支撑电路的深沟槽电容器和栅极电介质（绝缘体）
公开(公告)号：US06563160B2
公开(公告)日：2003-05-13
申请号：US09924549
申请日：2001-08-09
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L2994
CPC分类号： H01L29/945 , H01L21/28194 , H01L21/31604 , H01L21/3162 , H01L27/10829 , H01L27/1087 , H01L29/517 , H01L29/66181
摘要： A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.
摘要翻译：用于改进的DRAM（动态随机存取存储器）电介质结构的方法和结构，由此为用作栅极电介质的支撑器件以及电容器电介质实现新的高k材料。该方法形成用于电容器器件的深的隔离沟槽区域和用于支持器件的浅隔离沟槽区域。该方法还形成两个不同的绝缘体层，其中具有均匀的高k介电常数的一个绝缘体层用于深沟槽区域和支撑区域。另一个绝缘体层用于浅沟槽区域之间的阵列区域。

84. 发明授权

US06933189B2 Integration system via metal oxide conversion 失效
标题翻译：集成系统通过金属氧化物转换
公开(公告)号：US06933189B2
公开(公告)日：2005-08-23
申请号：US10870382
申请日：2004-06-16
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L21/285 , H01L21/30 , H01L21/306 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8232 , H01L21/8234 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/84 , H01L31/062 , H01L31/107 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28518 , H01L21/28568 , H01L21/3003 , H01L21/76823 , H01L21/76895 , H01L29/517 , H01L29/7833
摘要： A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.
摘要翻译：晶体管器件的方法和结构包括在衬底中形成源极，漏极和沟槽区域，在衬底上形成第一绝缘体，在第一绝缘体之上形成栅电极，形成邻接电极的一对绝缘衬垫，转换将所述第一绝缘体的一部分转变为金属膜，将所述金属膜转化成硅化物和自对隔硅膜之一，在所述沟槽区上方形成互连区，在所述第一绝缘体上方形成蚀刻停止层，所述沟槽区，所述栅电极和一对绝缘间隔物，在蚀刻停止层上方形成第二绝缘体，并在第二绝缘体中形成接触。第一绝缘体包括金属氧化物材料，其包括HfO x x和ZrO x x之一。

85. 发明授权

US07023528B2 Hybrid electronic mask 有权
标题翻译：混合电子面具
公开(公告)号：US07023528B2
公开(公告)日：2006-04-04
申请号：US10167327
申请日：2002-06-10
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： G03B27/72 , G03B27/54 , G03B27/42
CPC分类号： G03F1/26 , G03F7/2014 , G03F7/70291
摘要： An electronically programmable mask for lithography has an array of individually controllable light sources aligned with an array of individually controllable liquid crystals, so that individual pixels may be turned on or off and phase-shifted to provide a desired light intensity distribution on a wafer. The mask may be used in a contact printing mode or in a reduction projection mode.
摘要翻译：用于光刻的电子可编程掩模具有与独立可控液晶阵列对准的独立可控光源的阵列，使得各个像素可以被导通或截止并相移以在晶片上提供期望的光强分布。掩模可以以接触印刷模式或缩小投影模式使用。

86. 发明授权

US06670234B2 Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof 失效
标题翻译：将易失性和非易失性存储单元集成在同一衬底上的方法及其半导体存储器件
公开(公告)号：US06670234B2
公开(公告)日：2003-12-30
申请号：US09887403
申请日：2001-06-22
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang
IPC分类号： H01L2100
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10861 , H01L27/10894 , H01L27/11546
摘要： A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.
摘要翻译：在单个芯片上制造DRAM和闪存单元的方法包括提供硅衬底，为硅衬底中的每个DRAM单元形成沟槽电容器，形成硅衬底中彼此电隔离的隔离区域，形成通过在第一预定区域中注入第一种类型的杂质，在第一种类型的阱中的第二预定区域形成用于DRAM和闪速存储单元的第二类型阱，通过植入在第二预定区域中形成第二类型杂质，在第二类型阱上形成用于DRAM和闪存单元的氧化物层，在DRAM和闪存单元的氧化物层上形成用于DRAM的闪存存储单元的栅电极，以及形成源极和漏极用于DRAM和闪速存储器单元的相应的第二类型阱中的用于DRAM和闪存单元的区域 e源极和漏极区域与用于DRAM和闪存单元的每个栅电极相关联。

87. 发明授权

US06509612B2 High dielectric constant materials as gate dielectrics (insulators) 失效
公开(公告)号：US06509612B2
公开(公告)日：2003-01-21
申请号：US09848431
申请日：2001-05-04
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L2976
CPC分类号： H01L21/28176 , H01L21/26506 , H01L21/26586 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： A method and structure for a metal oxide semiconductor field effect transistor (MOSFET) includes patterning a gate stack (having a gate conductor layer and a gate dielectric) over a substrate and modifying the gate dielectric beneath the gate conductor, such that the gate dielectric has a central portion and modified dielectric regions adjacent the central portion. The modified dielectric regions have a lower dielectric constant than that of the gate dielectric and the central portion is shorter than the gate conductor.

88. 发明授权

US06452110B1 Patterning microelectronic features without using photoresists 失效
标题翻译：图案化微电子特征，而不使用光致抗蚀剂
公开(公告)号：US06452110B1
公开(公告)日：2002-09-17
申请号：US09897889
申请日：2001-07-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
IPC分类号： H05K109
CPC分类号： H05K3/02 , H01L21/288 , H01L21/32134 , H01L21/76885 , Y10T29/49155 , Y10T29/49156
摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.
摘要翻译：一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。

89. 发明授权

US06441421B1 High dielectric constant materials forming components of DRAM storage cells 失效
标题翻译：形成DRAM存储单元组件的高介电常数材料
公开(公告)号：US06441421B1
公开(公告)日：2002-08-27
申请号：US09858485
申请日：2001-05-17
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Joseph F. Shepard, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/1085 , H01L27/10861 , H01L27/10867 , H01L27/10873 , H01L27/1203 , H01L28/55
摘要： A method and structure for simultaneously producing a dynamic random access memory device and associated transistor is disclosed. The method forms channel regions and capacitor openings in a substrate. Next, the invention deposits capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel region and above the capacitor conductor. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.
摘要翻译：公开了一种用于同时产生动态随机存取存储器件和相关晶体管的方法和结构。该方法在衬底中形成通道区域和电容器开口。接下来，本发明在电容器开口中沉积电容器导体。然后，本发明同时在沟道区域上方和电容器导体之上形成单个绝缘体层。该单个绝缘体层包括在电容器导体上方的电容器节点电介质，并且在沟道区域上方包括栅极电介质。

90. 发明授权

US08802990B2 Self-aligned nano-scale device with parallel plate electrodes 有权
标题翻译：具有平行平板电极的自对准纳米级装置
公开(公告)号：US08802990B2
公开(公告)日：2014-08-12
申请号：US13432037
申请日：2012-03-28
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： H01B5/14 , H01L21/76 , H01L21/764
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

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