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81. 发明授权

US06841883B1 Multi-dice chip scale semiconductor components and wafer level methods of fabrication 失效
标题翻译：多芯片尺寸半导体元件和晶圆级制造方法
公开(公告)号：US06841883B1
公开(公告)日：2005-01-11
申请号：US10403937
申请日：2003-03-31
申请人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
发明人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
IPC分类号： H01L21/56 , H01L21/60 , H01L21/768 , H01L21/98 , H01L23/31 , H01L23/48 , H01L25/065 , H01L29/40
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
摘要翻译：半导体部件包括基模和层叠在基模上的二次模。基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板终端接触。一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

82. 发明授权

US06641175B2 Ramp-lock fitting device 失效
公开(公告)号：US06641175B2
公开(公告)日：2003-11-04
申请号：US10161290
申请日：2002-06-03
申请人： Kyle K. Kirby
发明人： Kyle K. Kirby
IPC分类号： F16L3500
CPC分类号： F16L49/06 , F16L37/113 , Y10S285/906 , Y10S285/911
摘要： A ramp-lock quick-connect fitting is adapted to be placed between conventional type fittings on pipes and tubes, such as quartz pipes and synthetic resin tubes used in chemical processing systems for semiconductor device fabrication. The quick-connect fitting includes a first coupling member having a pipe receiving section adapted to receive a conventional fitting on a pipe, and a ramp support section with a pair of spiral ramps formed therearound. The quick-connect fitting also includes a second coupling member that sealingly engages the first coupling member. An extension portion of the second coupling member is adapted to receive a conventional fitting on a tube. A locking collar is movably engaged with the second coupling member and has a pair of lock members disposed on an interior surface of the collar that slidably engage with the spiral ramps when the collar is rotated around the ramp support section of the first coupling member.

83. 发明授权

US08629057B2 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods 有权
标题翻译：具有单一通孔和通孔端子的半导体衬底，以及相关系统和方法
公开(公告)号：US08629057B2
公开(公告)日：2014-01-14
申请号：US13241059
申请日：2011-09-22
申请人： Kyle K. Kirby , Kunal R. Parekh
发明人： Kyle K. Kirby , Kunal R. Parekh
IPC分类号： H01L21/4763
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.
摘要翻译：公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时防止施加保护涂层的去除衬底材料。该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

84. 发明授权

US08410612B2 Interconnect regions 有权
标题翻译：互连区域
公开(公告)号：US08410612B2
公开(公告)日：2013-04-02
申请号：US13607407
申请日：2012-09-07
申请人： Kyle K. Kirby , Philip J. Ireland
发明人： Kyle K. Kirby , Philip J. Ireland
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/7682 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
摘要翻译：一些实施例包括互连区域。这些区域可以沿着横截面包含其中具有导电材料的封闭形状的内部区域，被配置为完全围绕内部区域的侧边缘延伸的衬垫的第一介电材料和至少两个介电突起，电介质材料衬里并且在内部区域的横向外侧。电介质突起可以具有围绕内部电介质区域的外部介电环。外环可以由第一介电材料组成，并且内介电区可以是不同于第一介电材料的组成的组成，在一些实施例中，内介电区内的组成可以是气态的。

85. 发明授权

US08404521B2 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods 有权
标题翻译：使用直通3D互连和相关系统和方法禁用电气连接
公开(公告)号：US08404521B2
公开(公告)日：2013-03-26
申请号：US13572461
申请日：2012-08-10
申请人： Michael Chaine , Kyle K. Kirby , William M. Hiatt , Russell D. Slifer
发明人： Jeffery W. Janzen , Michael Chaine , Kyle K. Kirby , William M. Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L21/50 , H01L21/76898 , H01L21/82 , H01L23/52 , H01L23/525 , H01L23/60 , H01L23/62 , H01L24/17 , H01L25/0657 , H01L25/50 , H01L27/0248 , H01L2224/02372 , H01L2224/0401 , H01L2224/13009 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17051 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/13034 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
摘要翻译：本文公开了直通3D互连和微电子管芯以及包括这种互连以禁用电连接的堆叠管芯的系统。在一个实施例中，堆叠管芯的系统包括具有背面的第一微电子管芯，经由第一管芯延伸到背面的互连件，电耦合到互连的集成电路，以及与第一静电放电（ESD）器件电隔离的第一静电放电互连。第二微电子管芯具有耦合到第一管芯的背侧的前侧，电连接到互连的前侧的金属接触件和电耦合到金属接触件的第二ESD器件。在另一实施例中，第一管芯还包括承载集成电路和第一ESD器件的衬底，并且互连件位于衬底中，以禁止第一ESD器件和互连件之间的电连接。

86. 发明授权

US08084866B2 Microelectronic devices and methods for filling vias in microelectronic devices 有权
标题翻译：用于在微电子器件中填充通孔的微电子器件和方法
公开(公告)号：US08084866B2
公开(公告)日：2011-12-27
申请号：US10733226
申请日：2003-12-10
申请人： William M. Hiatt , Kyle K. Kirby
发明人： William M. Hiatt , Kyle K. Kirby
IPC分类号： H01L23/52
CPC分类号： H01L24/14 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/45099 , H01L2224/48091 , H01L2224/48145 , H01L2225/06506 , H01L2225/06541 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
摘要翻译：本文公开了用于在微特征工件和模具中填充通孔并形成导电互连的微电子器件和方法。在一个实施例中，一种方法包括提供具有多个模具的微特征工件和从微特征工件的第一侧延伸穿过微特征工件的至少一个通道到微特征工件的相对的第二侧。该方法还可以包括在邻近微电子工件的第一侧的通道中形成导电插塞，以及在通道中沉积导电材料，以至少大体上填充从导电插头到微电子工件的第二侧的通道。

87. 发明授权

US08084854B2 Pass-through 3D interconnect for microelectronic dies and associated systems and methods 有权
标题翻译：用于微电子管芯的直通3D互连及相关系统和方法
公开(公告)号：US08084854B2
公开(公告)日：2011-12-27
申请号：US11966824
申请日：2007-12-28
申请人： David S. Pratt , Kyle K. Kirby , Dewali Ray
发明人： David S. Pratt , Kyle K. Kirby , Dewali Ray
IPC分类号： H01L23/04
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/043 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/051 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2924/01019 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.
摘要翻译：本文公开了直通3D互连和包括这种互连的堆叠管芯的微电子管芯和系统。在一个实施例中，堆叠管芯的系统包括具有衬底，金属衬底焊盘和电耦合到衬底焊盘的第一集成电路的第一微电子管芯。直通3D互连在衬底的前侧和后侧之间延伸，包括通过衬底焊盘。所述直通互连件与所述衬底焊盘电隔离并且电耦合到附接到所述衬底的背侧的第二微电子管芯的第二集成电路。在另一个实施例中，第一集成电路是第一存储器件，第二集成电路是第二存储器件，并且系统使用直通互连作为到第二存储器件的独立通信路径的一部分。

88. 发明申请

US20110287572A1 SEMICONDUCTOR DEVICE FABRICATION METHODS 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20110287572A1
公开(公告)日：2011-11-24
申请号：US13198533
申请日：2011-08-04
申请人： Kyle K. Kirby , Steve Oliver
发明人： Kyle K. Kirby , Steve Oliver
IPC分类号： H01L31/18 , H01L21/02
CPC分类号： H01L27/14636 , H01L21/76898 , H01L27/14612 , H01L27/14625 , H01L27/14632 , H01L27/14643
摘要： Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.
摘要翻译：用于制造诸如互补金属氧化物半导体（CMOS）成像器的半导体器件的方法包括在制造衬底的有源表面上制造晶体管和其它低仰角特征，以及制造接触插塞，导线，外部触点等在制造基板的背面上的较高高度特征。还公开了在有源表面上具有晶体管的半导体器件和延伸穿过衬底的接触插塞，以及包括这种半导体器件的电子器件也是公开的。

89. 发明授权

US08030780B2 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods 有权
标题翻译：具有单一通孔和通孔端子的半导体衬底，以及相关系统和方法
公开(公告)号：US08030780B2
公开(公告)日：2011-10-04
申请号：US12253121
申请日：2008-10-16
申请人： Kyle K. Kirby , Kunal R. Parekh
发明人： Kyle K. Kirby , Kunal R. Parekh
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/06181 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06544 , H01L2225/06548 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.
摘要翻译：公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时防止施加保护涂层的去除衬底材料。该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

90. 发明申请

US20110136336A1 METHODS OF FORMING CONDUCTIVE VIAS 有权
标题翻译：形成导电VIAS的方法
公开(公告)号：US20110136336A1
公开(公告)日：2011-06-09
申请号：US13029950
申请日：2011-02-17
申请人： Salman Akram , William Mark Hiatt , Steven Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steven Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.
摘要翻译：形成导电通孔的方法可以包括部分地穿过衬底形成盲孔，在衬底的表面上形成铝膜，从一些表面去除铝膜的第一部分，将导电材料选择性地沉积到第二部分上铝膜，并且通过基板的背面露出盲孔。制造导电通孔的方法可以包括通过至少一个未镀覆的焊盘形成至少一个通孔，在至少一个通孔的至少一个表面上形成第一粘合剂，在第一粘合剂上形成电介质，形成基底层叠在电介质和至少一个未镀覆的焊盘上，并将镍镀在基底层上。

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