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81. 发明申请

US20090238926A1 MILK-TYPE FOOD AND DRINK PACKED IN TRANSPARENT CONTAINER AND PROCESS FOR PRODUCING THE SAME 有权
标题翻译：包装在容器中的奶类食品和饮料及其生产方法
公开(公告)号：US20090238926A1
公开(公告)日：2009-09-24
申请号：US12094432
申请日：2006-11-20
申请人： Tomokazu Hara , Tomoyasu Taguchi , Yasushi Kubota
发明人： Tomokazu Hara , Tomoyasu Taguchi , Yasushi Kubota
IPC分类号： A23C3/00 , B65D85/72 , A23C7/04
CPC分类号： B65D81/30 , A23C3/005 , A23G9/00 , B65D65/20 , B65D85/80
摘要： An object of the present invention is to provide a milk-type food and drink including cow's milk packed in a transparent container such as a PET bottle, which does not generate off-flavor due to photoinduction even when the milk-type food and drink is a store-displaying commercial product which is apt to come under the influence of sunlight and fluorescent light. The invention relates to a milk-type food and drink packed in a transparent container which substantially shields light in the wavelength region of 550 to 720 nm, and a process for producing a milk-type food and drink, which comprises packing a milk-type food and drink in a transparent container which substantially shields light in the wavelength region of 550 to 720 nm.
摘要翻译：本发明的目的是提供一种包含牛奶的奶类食品和饮料，其包装在诸如PET瓶的透明容器中，即使当乳型食品和饮料是一种容易受到阳光和荧光灯影响的商店展示商品。本发明涉及一种包装在透明容器中的乳状食品和饮料，其基本上屏蔽了550-720nm的波长范围的光，以及一种生产牛奶型食品和饮料的方法，包括将牛奶型在透明容器中食物和饮料，其基本上屏蔽在550至720nm的波长区域中的光。

82. 发明授权

US07460099B2 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US07460099B2
公开(公告)日：2008-12-02
申请号：US10949990
申请日：2004-09-23
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

83. 发明申请

US20080150924A1 Signal processing circuit, low-voltage signal generator and image display incorporating the same 有权
标题翻译：信号处理电路，低压信号发生器和包含其的图像显示
公开(公告)号：US20080150924A1
公开(公告)日：2008-06-26
申请号：US12071529
申请日：2008-02-21
申请人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
发明人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G06F3/038 , H03K19/0175
CPC分类号： G09G3/3688 , G09G3/20 , G09G2310/0289 , G09G2330/021
摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
摘要翻译：提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到传输系统。在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

84. 发明授权

US07365727B2 Two-way shift register and image display device using the same 失效
标题翻译：双向移位寄存器和图像显示装置使用相同
公开(公告)号：US07365727B2
公开(公告)日：2008-04-29
申请号：US10788161
申请日：2004-02-25
申请人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
发明人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G09G2310/0283 , G09G2310/0289 , G09G2330/021 , G11C19/28
摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.
摘要翻译：移位寄存器具有移位寄存器部分，该移位寄存器部分由与时钟信号同步操作的多级触发器组成;以及电平移位器，用于升压低于驱动电压的启动信号，并将其施加到两端的移位寄存器，并且移位寄存器能够根据切换信号切换移位方向。上述电平移位器是电流驱动型电平移位器，即使在晶体管特性较差的情况下或者在快速操作的情况下也能够工作，并且即使利用具有小振幅的启动信号也能进行电平移位。此外，上述电平移位器分别设置在移位寄存器部分的两端，并且其中一个电平移位器根据切换信号停止工作，从而消耗的功率应该减小。因此，可以提供能够在两个方向上移位的移位寄存器，即使在具有小幅度的输入信号的情况下也能正常地进行操作，因此消耗较少的电力。

85. 发明授权

US07358950B2 Signal processing circuit, low-voltage signal generator, and image display incorporating the same 有权
标题翻译：信号处理电路，低电压信号发生器和包含其的图像显示器
公开(公告)号：US07358950B2
公开(公告)日：2008-04-15
申请号：US10145905
申请日：2002-05-16
申请人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
发明人： Hidehiko Yamashita , Hajime Washio , Yasushi Kubota , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/20 , G09G2310/0289 , G09G2330/021
摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
摘要翻译：提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到传输系统。在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

86. 发明授权

US07193604B2 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
标题翻译：移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法
公开(公告)号：US07193604B2
公开(公告)日：2007-03-20
申请号：US11060963
申请日：2005-02-18
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译：移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路线和多个锁存电路。在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

87. 发明申请

US20060057271A1 Method for producing good-flavor butter milk associated dairy product and dairy processed product 有权
标题翻译：生产高档奶油乳制品和乳制品加工产品的方法
公开(公告)号：US20060057271A1
公开(公告)日：2006-03-16
申请号：US10538298
申请日：2003-12-10
申请人： Yasushi Kubota , Yukinari Takeuchi , Satoshi Hayashi , Naoki Orii , Tadashi Nakatsubo
发明人： Yasushi Kubota , Yukinari Takeuchi , Satoshi Hayashi , Naoki Orii , Tadashi Nakatsubo
IPC分类号： A23C21/00
CPC分类号： A23C9/1524 , A23C3/03 , A23C17/00 , A23C2240/20
摘要： A process for preparing butter milk and/or butter serum, which comprises decreasing the dissolved oxygen concentration of at least one selected from the group consisting of milk, a milk product, butter milk and butter serum, followed by heating, and optionally fractionizing the heated product.
摘要翻译：一种制备奶油和/或黄油血清的方法，其包括降低选自牛奶，奶制品，奶油和黄油血清中的至少一种的溶解氧浓度，然后加热，并且任选地将加热的产品。

88. 发明申请

US20050248381A1 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US20050248381A1
公开(公告)日：2005-11-10
申请号：US11103893
申请日：2005-04-12
申请人： Yasushi Kubota , Masahiro Sato , Hiroshi Watanabe
发明人： Yasushi Kubota , Masahiro Sato , Hiroshi Watanabe
IPC分类号： H03K19/0185 , H03K3/356 , H03K17/22 , H03L5/00
CPC分类号： H03K3/356113 , H03K17/223
摘要： The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. :evel shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.
摘要翻译：电路是提供一种类型的电平移位电路，即使当来自多个电源的电压的输入定时不同时也能正常工作。：作为对低电压源的输入信号的响应而输出高电压源的输出信号的电平移位电路10具有以下特性：当低电压源的馈电相对于高电压源的馈送而被延迟时基于高电压源，上电复位电路20产生上电复位信号PWR。在将低电压源的输入信号作为对上电复位PWR的响应进给之前的期间，锁存电路30初始化电平移位电路，并将其输出OUT保持在低电平。

89. 发明授权

US06791526B2 Drive circuit 有权
标题翻译：驱动电路
公开(公告)号：US06791526B2
公开(公告)日：2004-09-14
申请号：US10097784
申请日：2002-03-13
申请人： Yasushi Kubota , Tatsumi Satoh
发明人： Yasushi Kubota , Tatsumi Satoh
IPC分类号： G09G336
CPC分类号： G09G3/3685 , G09G2300/0408 , G09G2300/08 , G09G2310/0275 , G09G2310/0297 , G09G2310/06
摘要： A drive circuit, for example a gate line drive circuit for a TFT liquid-crystal display, having a circuit size smaller than in the past. A TFT drive circuit has the shifting direction of drive data sequentially shifted through shift registers (SR116-R60) and is further inverted by a control signal (SEL_SFT), and the data are shifted in the opposite direction, from the first shift register (SR61) to the second shift register (SR116). At this time, the upper group of switching circuits (SW1-SW56) or the lower group of switching circuits (SW116-SW61) is enabled and the other group is disabled by control signals (SEL_UP, SEL_LO). Once the drive data are shifted to the bits of the shift registers, a voltage selection signal generated by a decoder (DEn) is inputted to an output circuit via an effective switching circuit, and a drive signal for a TFT gate is outputted. The number of circuits is reduced because the shift registers (SR61-SR116) and decoders (DE61-DE116) are shared by two outputs.
摘要翻译：驱动电路，例如TFT液晶显示器的栅极线驱动电路，其电路尺寸比以往小。 TFT驱动电路具有通过移位寄存器（SR116-R60）顺序移位的驱动数据的移位方向，并且由控制信号（SEL_SFT）进一步反转，并且数据沿相反方向从第一移位寄存器（SR61 ）到第二移位寄存器（SR116）。此时，开关电路（SW1-SW56）或下组开关电路（SW116-SW61）被使能，另一组被控制信号（SEL_UP，SEL_LO）禁止。一旦驱动数据被移位到移位寄存器的位，由解码器（DEn）产生的电压选择信号通过有效的开关电路被输入到输出电路，并且输出用于TFT栅极的驱动信号。由于移位寄存器（SR61-SR116）和解码器（DE61-DE116）由两个输出共享，所以电路数量减少。

90. 发明授权

US06565117B2 Arrangement and construction of crew protective device for automobile 有权
公开(公告)号：US06565117B2
公开(公告)日：2003-05-20
申请号：US09928695
申请日：2001-08-14
申请人： Yasushi Kubota , Masamichi Aono , Goro Takahashi , Takuya Ohtsuka , Minoru Shibata , Yutaka Nagai , Hiroyuki Tajima , Fumitake Kobayashi , Hiroki Nakajima , Chiharu Totani , Tadao Tanaka , Katsunori Noto
发明人： Yasushi Kubota , Masamichi Aono , Goro Takahashi , Takuya Ohtsuka , Minoru Shibata , Yutaka Nagai , Hiroyuki Tajima , Fumitake Kobayashi , Hiroki Nakajima , Chiharu Totani , Tadao Tanaka , Katsunori Noto
IPC分类号： B60R2122
CPC分类号： B60R21/213 , B60R13/0206 , B60R13/025 , B60R13/06 , B60R21/215 , B60R21/216 , B60R2013/0281 , B60R2013/0287 , B60R2013/0293 , B60R2021/0414 , B60R2021/0435 , B60R2021/2163
摘要： A structure of arranging an vehicle occupant protecting apparatus for an automotive vehicle, which can prevent a pillar garnish from scattering when an air bag installed in a front pillar portion is expanded, is provided. An air bag 16 is housed within a space formed by a front pillar main body 38 and a pillar garnish 40 in a front pillar portion 20. When the air bag 16 expands, the pillar garnish 40 is pressed by an expanding pressure of the air bag 16, so that an opening for expanding the air bag 16 is formed between the front pillar main body 38 and the pillar garnish 40, and the air bag 16 expands into a vehicle cabin through the opening. Since a non-expanding portion is formed at the air bag 16 and a hinge portion 46 is formed at the pillar garnish 40, the expanding pressure applied to the pillar garnish 40 when the air bag 16 expand is low, so that the pillar garnish 40 can be easily opened through the hinge portion 46.

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