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81. 发明申请

US20100124095A1 Floating Source Line Architecture for Non-Volatile Memory 有权
标题翻译：非易失性存储器的浮动源线架构
公开(公告)号：US20100124095A1
公开(公告)日：2010-05-20
申请号：US12272507
申请日：2008-11-17
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00 , G11C11/416 , G11C8/08 , G11C11/02
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
摘要翻译：一种用于将数据写入诸如RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。源极线连接到开关器件，并将一系列存储器单元连接在一起。此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态剩余的RSE连接到所选择的源线。

82. 发明授权

US07606097B2 Array sense amplifiers, memory devices and systems including same, and methods of operation 有权
标题翻译：阵列读出放大器，包括其的存储器件和系统以及操作方法
公开(公告)号：US07606097B2
公开(公告)日：2009-10-20
申请号：US11646735
申请日：2006-12-27
申请人： Chulmin Jung , Tae Kim
发明人： Chulmin Jung , Tae Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C11/4091
摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.
摘要翻译：描述了具有减小的增益的放大器级的读出放大器。读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。

83. 发明授权

US07170806B2 Data path having grounded precharge operation and test compression capability 有权
标题翻译：具有接地预充电操作和测试压缩能力的数据通路
公开(公告)号：US07170806B2
公开(公告)日：2007-01-30
申请号：US11367467
申请日：2006-03-03
申请人： George Raad , Chulmin Jung
发明人： George Raad , Chulmin Jung
IPC分类号： G11C7/00
CPC分类号： G11C29/40 , G11C2029/1204
摘要： A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.
摘要翻译：用于在存储器单元和输入/输出（IO）线路读出放大器之间耦合数据的数据路径。 IO线耦合电路耦合到一对全局数据线和一对本地数据线，以根据用于存储器的本地数据线的电压电平将每个全局数据线耦合到电压源和从电压源分离读操作。对于存储器写入操作，IO线耦合电路将每个全局数据线耦合到每个本地数据线的相应的一个。数据路径还包括耦合到全局数据线的第一预充电电路，以将全局数据线耦合到地，以在存储器读或写操作之前对信号线进行预充电，并且还可以包括耦合到全局数据的测试压缩电路线条。

84. 发明申请

US20060158944A1 Data path having grounded precharge operation and test compression capability 有权
公开(公告)号：US20060158944A1
公开(公告)日：2006-07-20
申请号：US11367467
申请日：2006-03-03
申请人： George Raad , Chulmin Jung
发明人： George Raad , Chulmin Jung
IPC分类号： G11C7/00
CPC分类号： G11C29/40 , G11C2029/1204
摘要： A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

85. 发明授权

US07038954B2 Apparatus with equalizing voltage generation circuit and methods of use 失效
公开(公告)号：US07038954B2
公开(公告)日：2006-05-02
申请号：US10929202
申请日：2004-08-30
申请人： Chulmin Jung
发明人： Chulmin Jung
IPC分类号： G11C11/00
CPC分类号： G11C11/4094
摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.

86. 发明申请

US20060044930A1 APPARATUS WITH EQUALIZING VOLTAGE GENERATION CIRCUIT AND METHODS OF USE 失效
标题翻译：具有均衡电压发生电路的装置及其使用方法
公开(公告)号：US20060044930A1
公开(公告)日：2006-03-02
申请号：US10929202
申请日：2004-08-30
申请人： Chulmin Jung
发明人： Chulmin Jung
IPC分类号： G11C8/00
CPC分类号： G11C11/4094
摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.
摘要翻译：存储器件包括均衡电压发生器。均衡电压发生器包括振荡器和电荷泵以产生第一电压，其可以用作互补数字线对的均衡电压。振荡器由均衡电压发生器的反馈和控制回路产生的振荡器控制信号控制。反馈和控制回路包括参考发生器电路，以产生稳定的内部参考信号，其被钳位在最大参考电压。反馈和控制环路的比较器将内部参考信号与第一电压成比例的第二电压进行比较。当第二电压低于参考电压时，比较器使振荡器导通，并且当第二电压高于参考电压时使振荡器关断。

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