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81. 发明申请

US20120258544A1 Plasmonic Force Manipulation in Nanostructures 有权
标题翻译：纳米结构中的等离子体力学操作
公开(公告)号：US20120258544A1
公开(公告)日：2012-10-11
申请号：US13518570
申请日：2010-12-24
申请人： Chang Chen , Pol Van Dorpe , Kai Cheng , Tim Stakenborg , Liesbet Lagae
发明人： Chang Chen , Pol Van Dorpe , Kai Cheng , Tim Stakenborg , Liesbet Lagae
IPC分类号： G01N21/65
CPC分类号： B82Y15/00 , C12Q1/6869 , G01N33/48721 , G01N33/538 , Y10T436/143333 , C12Q2565/631 , C12Q2565/607
摘要： A system (100) is described for characterizing and/or manipulating molecules. The system may especially be suitable for biological molecules, although the invention is not limited thereto. The system (100) comprises a substrate (110) comprising a nanostructure (120) being suitable for translocation of molecules through the nanostructure (120). It furthermore comprises a means (210) for translocating molecules through the nanostructure (120) and a plasmonic force field generating means (130) adapted for influencing the translocation speed of the particle by applying a plasmonic force field at the nanostructure (120). A corresponding method also is described.
摘要翻译：描述了用于表征和/或操纵分子的系统（100）。该系统可以特别适用于生物分子，尽管本发明不限于此。该系统（100）包括一个衬底（110），该衬底（110）包括适合于通过纳米结构（120）的分子易位的纳米结构（120）。它还包括用于使分子转移通过纳米结构（120）的装置（210）和适于通过在纳米结构（120）处施加等离子体力场来影响颗粒的易位速度的等离子体激元场产生装置（130）。还描述了相应的方法。

82. 发明申请

US20120185706A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CONTROL OF ENERGY CONSUMPTION IN POWER DOMAINS 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括动力领域能源消耗的动态控制
公开(公告)号：US20120185706A1
公开(公告)日：2012-07-19
申请号：US13324932
申请日：2011-12-13
申请人： Krishnakanth V. Sistla , Martin T. Rowland , Cesar A. Quiroz , Joseph R. Doucette , Gopikrishna Jandhyala , Kai Cheng , Celeste M. Brown , Avinash N. Ananthakrishnan
发明人： Krishnakanth V. Sistla , Martin T. Rowland , Cesar A. Quiroz , Joseph R. Doucette , Gopikrishna Jandhyala , Kai Cheng , Celeste M. Brown , Avinash N. Ananthakrishnan
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3206
摘要： An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
摘要翻译：这里描述了用于动力域的动态功率控制的装置，方法和系统。提供了一个时间窗口的功率限制。在控制环路周期内，电源接口决定了电力领域的能源消耗，智能地根据能源消耗在电力领域的设备之间预算功率，将这些预算转换为电力域的性能最大值，并限制了电力领域的设备性能。功率域使用运行平均功率限制来达到性能最大值。

83. 发明授权

US08196037B2 Method and device for extracting web information 有权
标题翻译：用于提取Web信息的方法和设备
公开(公告)号：US08196037B2
公开(公告)日：2012-06-05
申请号：US12338484
申请日：2008-12-18
申请人： Kai Cheng
发明人： Kai Cheng
IPC分类号： G06F17/20
CPC分类号： G06F17/2247 , G06F17/227 , G06F17/30896
摘要： A method for extracting web information includes: selecting a number of Hypertext Markup Language, HTML, tags as tag ruler elements to generate a tag ruler from an HTML text of a web page according to sequence of the HTML text; matching the HTML text with the tag ruler elements in the tag ruler according to the sequence of the tag ruler elements in the tag ruler, segmenting web information according to matched HTML tags and saving web information segments and location information of HTML tags enclosing the web information segments in the HTML text; and determining location of HTML tags containing web information needed by a user in the HTML text, extracting web information segments corresponding to the web information needed by the user from the saved web information segments.
摘要翻译：一种用于提取网页信息的方法包括：根据HTML文本的顺序，从网页的HTML文本中选择多个超文本标记语言，HTML，标签作为标签标尺元素，以生成标签尺; 根据标签标尺中的标签标尺元素的顺序，将HTML文本与标签标尺中的标签标尺元素进行匹配，根据匹配的HTML标签分割网页信息，并保存包含网页信息的HTML标签的网页信息片段和位置信息 HTML文本中的段; 以及确定包含用户在HTML文本中所需的web信息的HTML标签的位置，从保存的web信息段中提取与用户所需的web信息相对应的web信息段。

84. 发明申请

US20110185101A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统
公开(公告)号：US20110185101A1
公开(公告)日：2011-07-28
申请号：US13076041
申请日：2011-03-30
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

85. 发明授权

US07984250B2 Dynamic updating of thresholds in accordance with operating conditons 有权
标题翻译：根据操作条件动态更新阈值
公开(公告)号：US07984250B2
公开(公告)日：2011-07-19
申请号：US12317965
申请日：2008-12-31
申请人： Robin Steinbrecher , Christian Le , Rahul Khanna , Fernando A. Lopez , Kai Cheng
发明人： Robin Steinbrecher , Christian Le , Rahul Khanna , Fernando A. Lopez , Kai Cheng
IPC分类号： G06F12/00
CPC分类号： G06F1/206 , G11C7/04
摘要： In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，存储器控制装置包括远离存储器件的传感器，用于存储偏移值的寄存器，对应于传感器的温度读数与存储器件的估计实际温度之差的偏移值，以及控制器，用于控制所述存储器件的操作，其中所述控制器被配置为从所述寄存器读取所述偏移值，并且根据所述偏移值来控制所述存储器件的操作。控制器可以被配置为在存储器设备的操作期间动态地更新偏移值。公开和要求保护其他实施例。

86. 发明授权

US07941618B2 Fully buffered DIMM read data substitution for write acknowledgement 有权
标题翻译：全缓冲DIMM读取数据替代写入确认
公开(公告)号：US07941618B2
公开(公告)日：2011-05-10
申请号：US12202088
申请日：2008-08-29
申请人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
发明人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
IPC分类号： G06F12/16
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

87. 发明授权

US07885914B2 Systems, methods and apparatuses for rank coordination 有权
标题翻译：秩序协调的系统，方法和装置
公开(公告)号：US07885914B2
公开(公告)日：2011-02-08
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于秩协调的系统，方法和装置。在一些实施例中，主机包括秩协调逻辑。秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。描述和要求保护其他实施例。

88. 发明申请

US20100005248A1 PSEUDO LEAST RECENTLY USED REPLACEMENT/ALLOCATION SCHEME IN REQUEST AGENT AFFINITIVE SET-ASSOCIATIVE SNOOP FILTER 有权
标题翻译： PSEUDO最近最近使用的替代/分配方案请求代理机构设置相关SNOOP过滤器
公开(公告)号：US20100005248A1
公开(公告)日：2010-01-07
申请号：US12558796
申请日：2009-09-14
申请人： Kai Cheng , David C. Lee , John A. Urbanski
发明人： Kai Cheng , David C. Lee , John A. Urbanski
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/082 , G06F12/0822 , G06F12/123
摘要： The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.
摘要翻译：窥探过滤器的存储位置被分离成多个组，并且一些组与系统中的一些处理器相关联。当新数据进入处理器的高速缓存行时，选择与处理器相关联的存储位置之一用于进一步的操作。

89. 发明申请

US20090300289A1 Reducing back invalidation transactions from a snoop filter 有权
标题翻译：从监听过滤器中减少无效事务
公开(公告)号：US20090300289A1
公开(公告)日：2009-12-03
申请号：US12156340
申请日：2008-05-30
申请人： Tsvika Kurts , Kai Cheng , Jeffrey D. Gilbert , Julius Mandelblat
发明人： Tsvika Kurts , Kai Cheng , Jeffrey D. Gilbert , Julius Mandelblat
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/082
摘要： In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从缓存代理接收待处理容量迁移的指示的方法，确定来自缓存代理的无效回写事务是否可能用于与待处理的容量迁移相关联的高速缓存行，并且如果是将与高速缓存行相关联的窥探过滤条目从窥探过滤器移动到暂存区域。描述和要求保护其他实施例。

90. 发明授权

US07484044B2 Method and apparatus for joint cache coherency states in multi-interface caches 失效
标题翻译：多接口缓存中联合高速缓存一致性状态的方法和装置
公开(公告)号：US07484044B2
公开(公告)日：2009-01-27
申请号：US10662093
申请日：2003-09-12
申请人： Jeffrey D. Gilbert , Kai Cheng
发明人： Jeffrey D. Gilbert , Kai Cheng
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/507
摘要： A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache coherency state. The joint cache coherency state may have a first state for the inner interface and a second state for the outer interface, where the second state has higher privilege than the first state. In one embodiment this may promote speculative invalidation. In other embodiments this may reduce snoop transactions on the inner interface.
摘要翻译：公开了一种用于高速缓存一致性状态的方法和装置。在一个实施例中，可跨两个接口访问的高速缓存，内部接口和外部接口可以具有联合高速缓存一致性状态。联合高速缓存一致性状态可以具有内部接口的第一状态和外部接口的第二状态，其中第二状态具有比第一状态更高的特权。在一个实施例中，这可以促进投机无效。在其他实施例中，这可以减少内部接口上的窥探事务。

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