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81. 发明授权

US06330330B2 External resistor and method to minimize power dissipation in DC holding circuitry for a communication system 有权
标题翻译：外部电阻和方法，以减少通信系统直流保持电路中的功耗
公开(公告)号：US06330330B2
公开(公告)日：2001-12-11
申请号：US09737425
申请日：2000-12-15
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04M100
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06 , H04M19/001 , H04M19/02
摘要： A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.
摘要翻译：公开了用于直接存取布置（DAA）电路中的DC保持电路的CMOS实现，其提供期望的电感性能，同时最小化CMOS集成电路所需的功率耗散，特别是在高回路电流下。所公开的直流保持电路可以包括位于CMOS集成电路上的MOS晶体管和用于耗散CMOS集成电路外部的功率的片外功耗电阻器。所公开的CMOS实现还允许用于绘制DC电流的路径来为CMOS集成电路中的其他CMOS电路（例如ADC和DAC）供电。

82. 发明授权

US06327647B1 Method and apparatus for interfacing a processor to a coprocessor 有权
标题翻译：将处理器与协处理器进行接口的方法和装置
公开(公告)号：US06327647B1
公开(公告)日：2001-12-04
申请号：US09609260
申请日：2000-06-30
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F1500
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
摘要翻译：支持多个协处理器（14,16）的协处理器（14）接口的处理器（12）利用编译器可产生的软件类型函数调用和返回，指令执行以及可变加载和存储接口指令。数据在双向共享总线（28）上的处理器（12）和协处理器（14）之间隐含地通过寄存器窥探和广播来移动，或通过功能调用和返回以及可变负载和存储接口指令明确地移动。加载和存储接口指令允许选择性存储器地址预增量。双向总线（28）可以在每个时钟周期两方面潜在地驱动。接口分离接口指令解码和执行。通过在执行信号被断言之前否定解码信号来指示解码的指令丢弃来提供流水线操作。

83. 发明授权

US06298133B1 Telephone line interface architecture using ringer inputs for caller ID data 失效
标题翻译：电话线路接口架构，使用振铃器输入用于呼叫者ID数据
公开(公告)号：US06298133B1
公开(公告)日：2001-10-02
申请号：US09034802
申请日：1998-03-04
申请人： Jerrell P. Hein , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jerrell P. Hein , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04M1738
CPC分类号： H04L25/06 , H04L7/033 , H04L25/0266 , H04M1/573 , H04M11/06 , H04M19/001 , H04M19/02
摘要： A capacitive interface may be utilized to provide a linear output from the TIP and RING phone lines to ringer circuitry. Because the interface provides a linear signal, the input provided to the ringer circuitry may also be utilized for other functions in addition to ringer detection functions. More particularly, the outputs of the capacitive interface may also be connected to caller ID circuitry input lines so as to also provide caller ID data. The use of common inputs for the ringer circuitry and the caller ID circuitry eliminates the need for a separate caller ID interface.
摘要翻译：可以使用电容接口来提供从TIP和RING电话线到振铃电路的线性输出。由于接口提供线性信号，除了振铃检测功能之外，提供给振铃器电路的输入也可用于其它功能。更具体地，电容接口的输出也可以连接到主叫用户ID电路输入线，以便也提供呼叫者ID数据。使用通用输入用于振铃器电路和呼叫者ID电路消除了对单独的呼叫者ID接口的需要。

84. 发明授权

US06297755B2 Analog isolation system with digital communication across a capacitive barrier 有权
标题翻译：模拟隔离系统，通过电容屏障进行数字通讯
公开(公告)号：US06297755B2
公开(公告)日：2001-10-02
申请号：US09792940
申请日：2001-02-26
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H03M302
CPC分类号： H04B14/062 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.
摘要翻译：提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。最后，提供双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。

85. 发明授权

US06237089B1 Method and apparatus for affecting subsequent instruction processing in a data processor 有权
标题翻译：影响数据处理器中后续指令处理的方法和装置
公开(公告)号：US06237089B1
公开(公告)日：2001-05-22
申请号：US09425469
申请日：1999-10-22
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F900
CPC分类号： G06F9/30094 , G06F9/30079 , G06F9/30087 , G06F9/4812
摘要： A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.
摘要翻译：一种方法和装置影响数据处理器（10）中的后续指令处理。在一个实施例中，延迟中断识别指令（IDLY4）由数据处理器（10）执行以延迟或有条件地延迟中断识别，以控制间隔一段预定的时间段或预定数量的指令，使得可以在没有定义修改操作的专用指令的情况下执行读取/修改/写入指令序列。 IDLY4指令可能会影响后续指令影响条件位（38）的方式。因此，可以使用条件位（38）来确定在执行IDLY4指令之后的中断非识别间隔期间是否发生异常处理。

86. 发明授权

US06191717B1 Analog isolation system with digital communication across a capactive barrier 有权
公开(公告)号：US06191717B1
公开(公告)日：2001-02-20
申请号：US09226253
申请日：1999-01-07
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H03M302
CPC分类号： H04B14/062 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M11/06
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

87. 发明授权

US6160885A Caller ID circuit powered through hookswitch devices 失效
标题翻译：来电显示电路通过钩开关设备供电
公开(公告)号：US6160885A
公开(公告)日：2000-12-12
申请号：US34620
申请日：1998-03-04
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H03M1/42 , H04L7/033 , H04L25/02 , H04L25/06 , H04M1/57 , H04M11/06 , H04M19/00 , H04M19/02 , H04M1/00
CPC分类号： H04L25/06 , H04L7/033 , H04L25/0266 , H04M1/573 , H04M11/06 , H04M19/001 , H04M19/02
摘要： The communication system disclosed herein allows for the hookswitch devices to draw loop current from the phone line in both on-hook and off-hook conditions. Thus, even though an on-hook condition occurs, current may be obtained through the hookswitch devices. This feature allows circuitry which operates during on-hook conditions to still receive power from the phone line. Moreover because the hookswitch devices are utilized for drawing power in both on-hook and off-hook conditions, the use of additional switches dedicated to drawing the power during on-hook conditions is not required. For example, loop current may be drawn from the phone line through the hookswitch devices to power circuits used to perform the on-hook caller ID function. The powered circuits may include for example analog to digital converters. The technique disclosed herein for drawing current through the hookswitch devices is particularly useful for communications systems which utilize a capacitive isolation barrier system.
摘要翻译：本文公开的通信系统允许钩开关装置在挂机和摘机状况下从电话线拉出环路电流。因此，即使发生挂机状态，也可以通过钩开关装置获得电流。此功能允许在挂机状态下运行的电路仍然可以从电话线路接收电力。此外，由于钩式开关装置用于在挂机和摘机状态下拉取电力，所以不需要使用专用于在挂机状态下拉电源的附加开关。例如，回路电流可以从电话线通过钩开关装置抽取到用于执行挂机呼叫者ID功能的电源电路。供电电路可以包括例如模数转换器。用于通过钩开关装置抽出电流的技术对于利用电容隔离屏障系统的通信系统是特别有用的。

88. 发明授权

US5220483A Tri-level capacitor structure in switched-capacitor filter 失效
标题翻译：开关电容滤波器中的三电平电容器结构
公开(公告)号：US5220483A
公开(公告)日：1993-06-15
申请号：US821034
申请日：1992-01-16
申请人： Jeffrey W. Scott
发明人： Jeffrey W. Scott
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/08 , H01L29/92 , H03H19/00
CPC分类号： H01L27/0805 , H01L28/40
摘要： A tri-level capacitor structure includes a first shielded metal layer (36) that is disposed between an upper metal layer (38) and a lower polysilicon layer (34). The shielded metal layer (36) is separated from the polysilicon layer (34) by an oxide layer (42), and the upper metal layer (38) is separated from the shielded layer (36) by an oxide layer (44). The upper metal layer (38) and the polysilicon layer (34) are connected together to a node (48) to form an Insensitive Node, whereas the shielded layer (36) is connected to a node (46) that is referred to as the Sensitive Node (S). The capacitor structure is operable to be connected in a switched-capacitor configuration in a lossy integrator, such that the Sensitive Node is connected to the virtual ground of a differential amplifier (50). The integrator utilizing this configuration would be comprised of at least one switched-capacitor (56) on the input that has the plates thereof connected between ground and either an input signal V.sub.IN or the inverting input of the differential amplifier (50) through control switches (62) and (64). The Sensitive Node associated with node (46) is connected to the switch (62) such that it is connected between ground and the inverting input of amplifier (50).
摘要翻译：三电平电容器结构包括设置在上金属层（38）和下多晶硅层（34）之间的第一屏蔽金属层（36）。屏蔽金属层（36）通过氧化物层（42）与多晶硅层（34）分离，并且上部金属层（38）通过氧化物层（44）与屏蔽层（36）分离。上金属层（38）和多晶硅层（34）一起连接到节点（48）以形成不敏感节点，而屏蔽层（36）连接到被称为敏感节点（S）。电容器结构可操作地以有损积分器的开关电容器配置连接，使得灵敏节点连接到差分放大器（50）的虚拟接地。利用这种配置的积分器将由输入上的至少一个开关电容器（56）组成，该至少一个开关电容器（56）通过控制开关（其中的至少一个开关电容器56）连接在地之间，其输入信号VIN或差分放大器（50）的反相输入端 62）和（64）。与节点（46）相关联的灵敏节点连接到开关（62），使得它连接在地和放大器（50）的反相输入端之间。

89. 发明授权

US5212659A Low precision finite impulse response filter for digital interpolation 失效
标题翻译：用于数字插值的低精度有限冲击响应滤波器
公开(公告)号：US5212659A
公开(公告)日：1993-05-18
申请号：US773044
申请日：1991-10-08
申请人： Jeffrey W. Scott , Donald A. Kerth , Shaochyi Lin
发明人： Jeffrey W. Scott , Donald A. Kerth , Shaochyi Lin
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0614 , H03H17/0671
摘要： A low precision Finite Impulse Response filter (FIR) is provided for filtering in a digital interpolation operation. The interpolation operation includes two steps, a sampling rate conversion operation for interspersing zeroes between samples in an input sequence and a filtering step of filtering out images that result from this operation. The filtering operation utilizes a FIR filter that utilizes low precision filter coefficients that are selected to tune the frequency response such that the low end frequency response including the pass band, the transition band, and the portion of the stop band immediately after the transition band provides a response equivalent to that commensurate with substantially higher precision FIR filter coefficients, with the high frequency end of the stop band gradually increasing. A second, low pass filter section is provided for filtering out the image energy that exists at the output of the FIR filter in the high frequency end of the stop band to provide an overall filter response that is commensurate to that utilizing substantially higher precision FIR coefficients in the filter section. The FIR filter coefficients utilized are restricted to the set of [-1, 0, +1] such that a multiplierless FIR filter can be realized. The FIR filter coefficients are obtained by processing the infinite FIR filter coefficients through a software delta-sigma quantizer which quantizes the output to the desired low precision FIR filter coefficients.
摘要翻译：提供了一种低精度有限脉冲响应滤波器（FIR），用于在数字插值操作中进行滤波。内插操作包括两个步骤：用于在输入序列中的样本之间散布零的采样率转换操作和滤除由该操作产生的图像的滤波步骤。滤波操作利用FIR滤波器，该FIR滤波器利用被选择来调谐频率响应的低精度滤波器系数，使得包括通带，过渡频带以及紧接在转换频带之后的阻带的部分的低端频率响应提供等效于具有与较高精度FIR滤波器系数相当的响应，阻带的高频端逐渐增加。提供了第二个低通滤波器部分，用于滤除存在于阻带的高频端中的FIR滤波器的输出处的图像能量，以提供与利用基本上更高精度的FIR系数的整体滤波器响应相匹配的整体滤波器响应在过滤器部分。所使用的FIR滤波器系数被限制为[-1,0，+1]的集合，使得可以实现无乘法FIR滤波器。 FIR滤波器系数通过软件delta-sigma量化器处理无限FIR滤波器系数来获得，该量化器将输出量化到期望的低精度FIR滤波器系数。

90. 发明申请

US20120204012A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 有权
标题翻译：基于数据处理系统中的错误检测模式的可配置管道
公开(公告)号：US20120204012A1
公开(公告)日：2012-08-09
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/312
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

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