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81. 发明授权

US08455979B2 Three dimensional integrated deep trench decoupling capacitors 失效
标题翻译：三维集成深沟槽去耦电容器
公开(公告)号：US08455979B2
公开(公告)日：2013-06-04
申请号：US13369460
申请日：2012-02-09
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

82. 发明授权

US08409989B2 Structure and method to fabricate a body contact 有权
标题翻译：制造身体接触的结构和方法
公开(公告)号：US08409989B2
公开(公告)日：2013-04-02
申请号：US12944174
申请日：2010-11-11
申请人： Chengwen Pei , Roger Allen Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger Allen Booth, Jr. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/72
CPC分类号： H01L29/49 , H01L21/743 , H01L21/823475 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.
摘要翻译：公开了一种在晶体管上制造体接触的结构和方法。该方法包括在处理晶片上形成具有晶体管的半导体结构。然后将结构反转，并移除手柄晶片。然后在倒置位置的晶体管上形成硅化物体接触。身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

83. 发明申请

US20120306049A1 METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE 有权
标题翻译：金属电镀电容器和改进的隔离和制造方法
公开(公告)号：US20120306049A1
公开(公告)日：2012-12-06
申请号：US13153538
申请日：2011-06-06
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/743 , H01L21/76283 , H01L27/0629 , H01L27/108 , H01L27/1087 , H01L27/1203 , H01L28/60 , H01L28/92 , H01L29/0649 , H01L29/66181
摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
摘要翻译：提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

84. 发明申请

US20120305998A1 HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY 有权
标题翻译：高密度记忆细胞使用横向外延
公开(公告)号：US20120305998A1
公开(公告)日：2012-12-06
申请号：US13118881
申请日：2011-05-31
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L29/92 , H01L27/10829 , H01L27/10861 , H01L27/1203
摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.
摘要翻译：在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

85. 发明授权

US08188528B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08188528B2
公开(公告)日：2012-05-29
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

86. 发明申请

US20110215412A1 STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION 失效
标题翻译：通过局部化工作来形成具有超级GIDL的结构和方法
公开(公告)号：US20110215412A1
公开(公告)日：2011-09-08
申请号：US12717375
申请日：2010-03-04
申请人： Chengwen Pei , Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
发明人： Chengwen Pei , Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L21/22
CPC分类号： H01L21/22 , H01L21/8238 , H01L27/092
摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.
摘要翻译：提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为适应平带，但不影响设备通道区域的功能。该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。通过离子注入或退火可形成局部功能调谐区域。

87. 发明授权

US07790530B2 Dual port gain cell with side and top gated read transistor 失效
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07790530B2
公开(公告)日：2010-09-07
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

88. 发明申请

US20100207179A1 DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING AN ASYMMETRIC TRANSISTOR AND A COLUMNAR CAPACITOR 有权
标题翻译：动态随机存取存储器单元，包括不对称晶体管和柱型电容器
公开(公告)号：US20100207179A1
公开(公告)日：2010-08-19
申请号：US12700807
申请日：2010-02-05
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chengwen Pei , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/823431 , H01L27/10823 , H01L27/1085 , H01L27/10876 , H01L27/10879 , H01L28/60 , H01L29/66795 , H01L29/785
摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.
摘要翻译：在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。掺杂半导体柱构成电容器的内部电极。在半导体鳍片和半导体柱上形成介电层和导电材料层。图案化导电材料层以形成用于电容器的外部电极和栅电极。可以进行单侧晕圈植入。源极和漏极区域形成在半导体鳍片中以形成存取晶体管。源极区域电连接到电容器的内部电极。存取晶体管和电容器共同构成DRAM单元。

89. 发明授权

US07732872B2 Integration scheme for multiple metal gate work function structures 失效
标题翻译：多金属门功能结构的集成方案
公开(公告)号：US07732872B2
公开(公告)日：2010-06-08
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Ramachandra Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

90. 发明授权

US07439149B1 Structure and method for forming SOI trench memory with single-sided strap 失效
标题翻译：用单面带形成SOI沟槽存储器的结构和方法
公开(公告)号：US07439149B1
公开(公告)日：2008-10-21
申请号：US11861704
申请日：2007-09-26
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

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