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81. 发明授权

US07315916B2 Scratch pad block 有权
标题翻译：划痕块块
公开(公告)号：US07315916B2
公开(公告)日：2008-01-01
申请号：US11016285
申请日：2004-12-16
申请人： Alan David Bennett , Sergey Anatolievich Gorobets
发明人： Alan David Bennett , Sergey Anatolievich Gorobets
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： In a memory array having a minimum unit of erase of a block, a scratch pad block is used to store data that is later written to another block. The data may be written to the scratch pad block with a low degree of parallelism and later written to another location with a high degree of parallelism so that it is stored with high density. Data may be temporarily stored in the scratch pad block until it can be more efficiently stored elsewhere. This may be when some other data is received. Unrelated data may be stored in the same page of a scratch pad block.
摘要翻译：在具有块的最小擦除单位的存储器阵列中，使用便笺块块来存储稍后写入另一块的数据。数据可以以低度的平行度写入到便签块块中，并且随后以高度并行度写入另一位置，使得其以高密度存储。数据可以临时存储在便签区块中，直到其可以更有效地存储在别处。这可能是在收到某些其他数据时。不相关的数据可能存储在暂存区块的同一页中。

82. 发明授权

US06898662B2 Memory system sectors 有权
标题翻译：内存系统部门
公开(公告)号：US06898662B2
公开(公告)日：2005-05-24
申请号：US10260181
申请日：2002-09-27
申请人： Sergey Anatolievich Gorobets
发明人： Sergey Anatolievich Gorobets
IPC分类号： G06F3/06 , G06F12/02 , G06F12/00
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0679 , G06F12/0246
摘要： An embodiment of the present invention includes a method of implementing the logical grouping of memory system sectors in a non-volatile memory system in order to increase the operational speed of the memory system, the method comprising allocating sets of contiguous logical sectors containing file data from a host system into logical groups; ensuring that a logical group includes fewer sectors than there are sector locations in a memory block in the non-volatile memory; aligning the logical groups with the clusters into which the host system organizes sectors containing file data; writing sectors within a logical group to contiguous locations within the non-volatile memory; organizing the on-volatile memory such that the corresponding sector in each logical group is written to a corresponding array within the memory; the arrangement being such that the reading then writing of a sector of a cluster to relocate it to a different location in the non-volatile memory takes place within the same array, thereby allowing concurrent relocation of all sectors in a logical group.
摘要翻译：本发明的实施例包括一种在非易失性存储器系统中实现存储器系统扇区的逻辑分组以提高存储器系统的操作速度的方法，所述方法包括：分配包含文件数据的连续逻辑扇区的集合，主机系统成逻辑组; 确保逻辑组包括比在非易失性存储器中的存储器块中的扇区位置更少的扇区; 将逻辑组与主机系统组织包含文件数据的扇区对齐; 将逻辑组内的扇区写入所述非易失性存储器内的相邻位置; 组织所述易失性存储器，使得每个逻辑组中的对应扇区被写入所述存储器内的相应阵列; 该布置使得读取然后写入群集的扇区以将其重新定位到非易失性存储器中的不同位置，发生在相同的阵列内，从而允许并行重新定位逻辑组中的所有扇区。

83. 发明授权

US08848445B2 System and method for minimizing write amplification while maintaining sequential performance using logical group striping in a multi-bank system 有权
标题翻译：用于最小化写入放大的系统和方法，同时在多存储体系统中使用逻辑组条带化来维持顺序性能
公开(公告)号：US08848445B2
公开(公告)日：2014-09-30
申请号：US13474055
申请日：2012-05-17
申请人： Steven T. Sprouse , Sergey Anatolievich Gorobets , William Wu , Alan Bennett , Marielle Bundukin
发明人： Steven T. Sprouse , Sergey Anatolievich Gorobets , William Wu , Alan Bennett , Marielle Bundukin
IPC分类号： G11C11/34
CPC分类号： G11C7/1015 , G06F12/0246 , G06F2212/7202 , G06F2212/7208 , G11C2216/14
摘要： A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.
摘要翻译：公开了一种用于在保持期望的顺序读写性能水平的同时降低写入放大的系统和方法。多银行闪存存储设备中的控制器可以接收用于写入多个闪存组的主机数据。控制器可以将多个逻辑组中的接收数据组织成大于物理页面并且小于物理块，并且利用该条带化因子将主机数据的写入交织到存储体。缓冲RAM与多存储体存储器的每个存储体相关联，其中缓冲器RAM的大小等于或大于多页逻辑组的大小。

84. 发明授权

US08843693B2 Non-volatile memory and method with improved data scrambling 有权
标题翻译：非易失性存储器和具有改进的数据加扰的方法
公开(公告)号：US08843693B2
公开(公告)日：2014-09-23
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/00 , G11C7/10 , G11C16/34 , G06F12/14
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的编程干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

85. 发明申请

US20140281132A1 METHOD AND SYSTEM FOR RAM CACHE COALESCING 审中-公开
标题翻译： RAM缓存的方法和系统
公开(公告)号：US20140281132A1
公开(公告)日：2014-09-18
申请号：US13838582
申请日：2013-03-15
申请人： Marielle Bundukin , King Ying Ng , Steven T. Sprouse , William Wu , Sergey Anatolievich Gorobets , Liam Parker , Alan David Bennett
发明人： Marielle Bundukin , King Ying Ng , Steven T. Sprouse , William Wu , Sergey Anatolievich Gorobets , Liam Parker , Alan David Bennett
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above.
摘要翻译：公开了一种用于在诸如RAM缓存的易失性存储器中聚合数据片段的系统和方法。该方法可以包括将多个数据片段存储在易失性存储器中，并且仅当已经接收到预定数量的数据片段并将其聚合成单个闪速写入命令时，才将闪存的单个写入操作开始。该方法还可以包括生成在单个条目中聚合用于聚合数据片段的所有二进制缓存索引信息的二进制缓存索引增量。具有非易失性存储器的存储器系统，被设计成至少存储与非易失性存储器的二进制高速缓存中管理的物理页面相等的数据片段数量的易失性存储器以及控制器。控制器可以被配置为执行将数据片段聚合成上述单个闪存写入操作的方法。

86. 发明授权

US08456919B1 Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder 有权
标题翻译：提供包括硬比特数据和软比特数据的数据到秩调制解码器的方法和装置
公开(公告)号：US08456919B1
公开(公告)日：2013-06-04
申请号：US13293988
申请日：2011-11-10
申请人： Seungjune Jeon , Sergey Anatolievich Gorobets
发明人： Seungjune Jeon , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G06F11/1072
摘要： A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.
摘要翻译：一种方法包括向秩调制解码器提供包括硬比特数据和软比特数据的数据。

87. 发明授权

US08364883B2 Scheduling of housekeeping operations in flash memory systems 有权
公开(公告)号：US08364883B2
公开(公告)日：2013-01-29
申请号：US12493500
申请日：2009-06-29
申请人： Alan David Bennett , Sergey Anatolievich Gorobets , Andrew Tomlin , Charles Schroter
发明人： Alan David Bennett , Sergey Anatolievich Gorobets , Andrew Tomlin , Charles Schroter
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7205
摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

88. 发明申请

US20120297122A1 Non-Volatile Memory and Method Having Block Management with Hot/Cold Data Sorting 有权
标题翻译：具有热/冷数据排序的块管理的非易失性存储器和方法
公开(公告)号：US20120297122A1
公开(公告)日：2012-11-22
申请号：US13468737
申请日：2012-05-10
申请人： Sergey Anatolievich Gorobets , Alan David Bennett , Tom Hugh Shippey , Liam Michael Parker , Yauheni Yaromenka , Steven T. Sprouse , William S. Wu , Marielle Bundukin
发明人： Sergey Anatolievich Gorobets , Alan David Bennett , Tom Hugh Shippey , Liam Michael Parker , Yauheni Yaromenka , Steven T. Sprouse , William S. Wu , Marielle Bundukin
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F3/068 , G06F2212/7202 , G06F2212/7211 , G11C2211/5641
摘要： A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.
摘要翻译：组织成闪存可擦除块的非易失性存储器根据分配给每个数据单元的温度对数据单元进行排序，其中较高的温度指示由于垃圾收集操作而导致的数据单元将遭受后续重写的更高概率。数据单元来自主机写入或来自重定位操作。根据其温度，将数据分类用于存储到不同的存储部分，例如SLC和MLC，或者分成不同的操作流。这允许以适合其温度的方式处理类似温度的数据，以便使重写最小化。数据单元的示例包括逻辑组和块。

89. 发明申请

US20120297111A1 Non-Volatile Memory And Method With Improved Data Scrambling 有权
标题翻译：非易失性存储器和改进的数据加扰方法
公开(公告)号：US20120297111A1
公开(公告)日：2012-11-22
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/02
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的程序干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

90. 发明授权

US08296498B2 Method and system for virtual fast access non-volatile RAM 有权
标题翻译：用于虚拟快速访问非易失性RAM的方法和系统
公开(公告)号：US08296498B2
公开(公告)日：2012-10-23
申请号：US11939318
申请日：2007-11-13
申请人： Sergey Anatolievich Gorobets , Niv Cohen , Russell R. Reynolds
发明人： Sergey Anatolievich Gorobets , Niv Cohen , Russell R. Reynolds
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page of stored data comprising an allocated data space addressable in a second increment of address, pointed to by an address pointer, and comprising obsolete data. The first increment of address is greater than the second increment of address. A portion of stored data in the page buffer may be updated with the data to form an updated page of data. Storage space for the updated page of data may be allocated. The updated page of data may be written to the allocated storage space. The address pointer may be updated with a location of the allocated storage space.
摘要翻译：一种将块的擦除的最小单位写入数据到非易失性存储器的方法，作为块的编程单元的页面可以将以地址的第一增量寻址的存储数据页从存储器读取为页面缓冲器，存储数据的页面包括以地址指针指向的地址的第二增量可寻址的分配的数据空间，并且包括过时的数据。地址的第一个增量大于地址的第二个增量。页面缓冲器中存储的数据的一部分可以用数据更新以形成更新的数据页面。可以分配更新的数据页面的存储空间。更新的数据页可以写入分配的存储空间。可以用分配的存储空间的位置更新地址指针。

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