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1. 发明申请

US20140281132A1 METHOD AND SYSTEM FOR RAM CACHE COALESCING 审中-公开
标题翻译： RAM缓存的方法和系统
公开(公告)号：US20140281132A1
公开(公告)日：2014-09-18
申请号：US13838582
申请日：2013-03-15
申请人： Marielle Bundukin , King Ying Ng , Steven T. Sprouse , William Wu , Sergey Anatolievich Gorobets , Liam Parker , Alan David Bennett
发明人： Marielle Bundukin , King Ying Ng , Steven T. Sprouse , William Wu , Sergey Anatolievich Gorobets , Liam Parker , Alan David Bennett
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above.
摘要翻译：公开了一种用于在诸如RAM缓存的易失性存储器中聚合数据片段的系统和方法。该方法可以包括将多个数据片段存储在易失性存储器中，并且仅当已经接收到预定数量的数据片段并将其聚合成单个闪速写入命令时，才将闪存的单个写入操作开始。该方法还可以包括生成在单个条目中聚合用于聚合数据片段的所有二进制缓存索引信息的二进制缓存索引增量。具有非易失性存储器的存储器系统，被设计成至少存储与非易失性存储器的二进制高速缓存中管理的物理页面相等的数据片段数量的易失性存储器以及控制器。控制器可以被配置为执行将数据片段聚合成上述单个闪存写入操作的方法。

2. 发明授权

US09176864B2 Non-volatile memory and method having block management with hot/cold data sorting 有权
标题翻译：具有热/冷数据排序的块管理的非易失性存储器和方法
公开(公告)号：US09176864B2
公开(公告)日：2015-11-03
申请号：US13468737
申请日：2012-05-10
申请人： Sergey Anatolievich Gorobets , Alan David Bennett , Tom Hugh Shippey , Liam Michael Parker , Yauheni Yaromenka , Steven T. Sprouse , William S. Wu , Marielle Bundukin
发明人： Sergey Anatolievich Gorobets , Alan David Bennett , Tom Hugh Shippey , Liam Michael Parker , Yauheni Yaromenka , Steven T. Sprouse , William S. Wu , Marielle Bundukin
IPC分类号： G06F12/00 , G06F12/02 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F3/068 , G06F2212/7202 , G06F2212/7211 , G11C2211/5641
摘要： A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.
摘要翻译：组织成闪存可擦除块的非易失性存储器根据分配给每个数据单元的温度对数据单元进行排序，其中较高的温度指示由于垃圾收集操作而导致的数据单元将遭受后续重写的更高概率。数据单元来自主机写入或来自重定位操作。根据其温度，将数据分类用于存储到不同的存储部分，例如SLC和MLC，或者分成不同的操作流。这允许以适合其温度的方式处理类似温度的数据，以便使重写最小化。数据单元的示例包括逻辑组和块。

3. 发明申请

US20120297122A1 Non-Volatile Memory and Method Having Block Management with Hot/Cold Data Sorting 有权
标题翻译：具有热/冷数据排序的块管理的非易失性存储器和方法
公开(公告)号：US20120297122A1
公开(公告)日：2012-11-22
申请号：US13468737
申请日：2012-05-10
申请人： Sergey Anatolievich Gorobets , Alan David Bennett , Tom Hugh Shippey , Liam Michael Parker , Yauheni Yaromenka , Steven T. Sprouse , William S. Wu , Marielle Bundukin
发明人： Sergey Anatolievich Gorobets , Alan David Bennett , Tom Hugh Shippey , Liam Michael Parker , Yauheni Yaromenka , Steven T. Sprouse , William S. Wu , Marielle Bundukin
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F3/068 , G06F2212/7202 , G06F2212/7211 , G11C2211/5641
摘要： A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.
摘要翻译：组织成闪存可擦除块的非易失性存储器根据分配给每个数据单元的温度对数据单元进行排序，其中较高的温度指示由于垃圾收集操作而导致的数据单元将遭受后续重写的更高概率。数据单元来自主机写入或来自重定位操作。根据其温度，将数据分类用于存储到不同的存储部分，例如SLC和MLC，或者分成不同的操作流。这允许以适合其温度的方式处理类似温度的数据，以便使重写最小化。数据单元的示例包括逻辑组和块。

4. 发明申请

US20120320679A1 SYSTEM AND METHOD FOR MINIMIZING WRITE AMPLIFICATION WHILE MAINTAINING SEQUENTIAL PERFORMANCE USING LOGICAL GROUP STRIPPING IN A MULTI-BANK SYSTEM 有权
标题翻译：在多银行系统中使用逻辑组分支维护顺序性能来最小化写入放大的系统和方法
公开(公告)号：US20120320679A1
公开(公告)日：2012-12-20
申请号：US13474055
申请日：2012-05-17
申请人： Steven T. Sprouse , Sergey Anatolievich Gorobets , William Wu , Alan Bennett , Marielle Bundukin
发明人： Steven T. Sprouse , Sergey Anatolievich Gorobets , William Wu , Alan Bennett , Marielle Bundukin
IPC分类号： G11C16/04
CPC分类号： G11C7/1015 , G06F12/0246 , G06F2212/7202 , G06F2212/7208 , G11C2216/14
摘要： A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.
摘要翻译：公开了一种用于在保持期望的顺序读写性能水平的同时降低写入放大的系统和方法。多银行闪存存储设备中的控制器可以接收用于写入多个闪存组的主机数据。控制器可以将多个逻辑组中的接收数据组织成大于物理页面并且小于物理块，并且利用该条带化因子将主机数据的写入交织到存储体。缓冲RAM与多存储体存储器的每个存储体相关联，其中缓冲器RAM的大小等于或大于多页逻辑组的大小。

5. 发明授权

US08848445B2 System and method for minimizing write amplification while maintaining sequential performance using logical group striping in a multi-bank system 有权
标题翻译：用于最小化写入放大的系统和方法，同时在多存储体系统中使用逻辑组条带化来维持顺序性能
公开(公告)号：US08848445B2
公开(公告)日：2014-09-30
申请号：US13474055
申请日：2012-05-17
申请人： Steven T. Sprouse , Sergey Anatolievich Gorobets , William Wu , Alan Bennett , Marielle Bundukin
发明人： Steven T. Sprouse , Sergey Anatolievich Gorobets , William Wu , Alan Bennett , Marielle Bundukin
IPC分类号： G11C11/34
CPC分类号： G11C7/1015 , G06F12/0246 , G06F2212/7202 , G06F2212/7208 , G11C2216/14
摘要： A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.
摘要翻译：公开了一种用于在保持期望的顺序读写性能水平的同时降低写入放大的系统和方法。多银行闪存存储设备中的控制器可以接收用于写入多个闪存组的主机数据。控制器可以将多个逻辑组中的接收数据组织成大于物理页面并且小于物理块，并且利用该条带化因子将主机数据的写入交织到存储体。缓冲RAM与多存储体存储器的每个存储体相关联，其中缓冲器RAM的大小等于或大于多页逻辑组的大小。

6. 发明申请

US20120297118A1 FAST TRANSLATION INDICATOR TO REDUCE SECONDARY ADDRESS TABLE CHECKS IN A MEMORY DEVICE 有权
标题翻译：快速翻译指示符，以减少存储器件中的二次地址表检查
公开(公告)号：US20120297118A1
公开(公告)日：2012-11-22
申请号：US13464426
申请日：2012-05-04
申请人： Sergey Anatolievich Gorobets , William Wu , Steven T. Sprouse
发明人： Sergey Anatolievich Gorobets , William Wu , Steven T. Sprouse
IPC分类号： G06F12/02
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0679 , G06F12/0223 , G06F12/10 , G06F12/1009
摘要： A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device.
摘要翻译：公开了一种用于减少检查辅助地址表和用于逻辑到物理转换任务的主地址表的需要的系统和方法。该方法可以包括生成快速转换指示符，例如逻辑组位图，指示辅助地址表中是否存在包含与特定逻辑地址相关的期望信息的条目。在与特定逻辑地址相关的主机请求时，存储设备可以检查位图以确定是否需要检索和解析辅助表。该系统可以包括具有RAM高速缓存存储器，闪存存储器和被配置为生成和维护至少一个快速转换指示符的存储设备，以减少在存储器的逻辑到物理地址转换操作期间检查辅助和主地址表的需要设备。

7. 发明授权

US09104327B2 Fast translation indicator to reduce secondary address table checks in a memory device 有权
标题翻译：快速翻译指示符，以减少存储设备中的辅助地址表检查
公开(公告)号：US09104327B2
公开(公告)日：2015-08-11
申请号：US13464426
申请日：2012-05-04
申请人： Sergey Anatolievich Gorobets , William Wu , Steven T. Sprouse
发明人： Sergey Anatolievich Gorobets , William Wu , Steven T. Sprouse
IPC分类号： G06F12/00 , G06F3/06 , G06F12/10 , G06F12/02
CPC分类号： G06F3/064 , G06F3/0611 , G06F3/0679 , G06F12/0223 , G06F12/10 , G06F12/1009
摘要： A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device.
摘要翻译：公开了一种用于减少检查辅助地址表和用于逻辑到物理转换任务的主地址表的需要的系统和方法。该方法可以包括生成快速转换指示符，例如逻辑组位图，指示辅助地址表中是否存在包含与特定逻辑地址相关的期望信息的条目。在与特定逻辑地址相关的主机请求时，存储设备可以检查位图以确定是否需要检索和解析辅助表。该系统可以包括具有RAM高速缓存存储器，闪存存储器和被配置为生成和维护至少一个快速转换指示符的存储设备，以减少在存储器的逻辑到物理地址转换操作期间检查辅助和主地址表的需要设备。

8. 发明申请

US20120297121A1 Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions 审中-公开
标题翻译：非易失性存储器和小逻辑组的方法分布在主动SLC和MLC内存分区中
公开(公告)号：US20120297121A1
公开(公告)日：2012-11-22
申请号：US13468720
申请日：2012-05-10
申请人： Sergey Anatolievich Gorobets , William S. Wu , Steven T. Sprouse
发明人： Sergey Anatolievich Gorobets , William S. Wu , Steven T. Sprouse
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C2211/5641
摘要： A non-volatile memory organized into flash erasable blocks receives data from host writes by first staging into logical groups before writing into the blocks. Each logical group contains data from a predefined set of order logical addresses and has a fixed size smaller than a block. The totality of logical groups are obtained by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within a range delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block and up to an order of magnitude higher than a typical size of a host write. In this way, excessive garbage collection due to operating a large logical group is avoided while the address space is reduced to minimize the size of a caching RAM.
摘要翻译：组织成闪存可擦除块的非易失性存储器通过在写入块之前先进入逻辑组，从主机写入中接收数据。每个逻辑组包含来自预定义的一组订单逻辑地址的数据，并且具有小于块的固定大小。通过将主机的逻辑地址空间划分为有序逻辑地址的非重叠子范围来获得逻辑组的总和，每个逻辑组在由至少一个页面的最小大小限定的范围内具有预定大小，并且在块中拟合至少两个逻辑组的最大大小，并且高达主机写入的典型大小高达一个数量级。以这种方式，避免了由于操作大的逻辑组而导致的过多垃圾收集，同时减少了地址空间以最小化缓存RAM的大小。

9. 发明申请

US20110153912A1 Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory 审中-公开
标题翻译：维持二进制非易失性存储器中多级非易失性存储器的更新
公开(公告)号：US20110153912A1
公开(公告)日：2011-06-23
申请号：US12642584
申请日：2009-12-18
申请人： Sergey Anatolievich Gorobets , William S. Wu , Shai Traister , Alexander Lyashuk , Steven T. Sprouse
发明人： Sergey Anatolievich Gorobets , William S. Wu , Shai Traister , Alexander Lyashuk , Steven T. Sprouse
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G11C11/5628 , G11C2211/5641 , G11C2211/5643
摘要： A method of operating a memory system is presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first portion, where data is stored in a binary format, and a second portion, where data is stored in a multi-state format. The controller manages the transfer of data to and from the memory system and the storage of data on the non-volatile memory circuit. The method includes receiving a first set of data and storing this first set of data in a first location in the second portion of the non-volatile memory circuit. The memory system subsequently receives updated data for a first subset of the first data set. The updated data is stored in a second location in the first portion of the non-volatile memory circuit, where the controller maintains a logical correspondence between the second location and the first subset of the first set of data.
摘要翻译：提出了一种操作存储系统的方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有以二进制格式存储数据的第一部分和第二部分，其中数据以多状态格式存储。控制器管理到存储器系统和从存储器系统传送数据以及将数据存储在非易失性存储器电路上。该方法包括接收第一组数据并将该第一组数据存储在非易失性存储器电路的第二部分中的第一位置。存储器系统随后接收第一数据集的第一子集的更新数据。更新的数据被存储在非易失性存储器电路的第一部分中的第二位置，其中控制器维持第一组数据的第二位置和第一子集之间的逻辑对应关系。

10. 发明授权

US08995183B2 Data retention in nonvolatile memory with multiple data storage formats 有权
标题翻译：数据保存在具有多种数据存储格式的非易失性存储器中
公开(公告)号：US08995183B2
公开(公告)日：2015-03-31
申请号：US13453921
申请日：2012-04-23
申请人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila
发明人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/349 , G11C2211/5641
摘要： In a nonvolatile memory that stores data in two or more different data storage formats, such as binary and MLC, a separation scheme is used to distribute blocks containing data in one data storage format (e.g. binary) so that they are separated by at least some minimum number of blocks using another data storage format (e.g. MLC).
摘要翻译：在将数据存储在诸如二进制和MLC之类的两种或多种不同数据存储格式的非易失性存储器中，分离方案用于分发包含一种数据存储格式（例如二进制）的数据的块，使得它们被至少一些使用其他数据存储格式的最小块数（例如MLC）。

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