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81. 发明授权

US5664117A Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer 失效
标题翻译：用于预取数据以在计算机中的两条总线之间的桥中加载缓冲器的装置和方法
公开(公告)号：US5664117A
公开(公告)日：1997-09-02
申请号：US603688
申请日：1996-01-20
申请人： Nilesh Shah , Jasmin Ajanovic , Dahmane Dahmani
发明人： Nilesh Shah , Jasmin Ajanovic , Dahmane Dahmani
IPC分类号： G06F5/06 , G06F13/40 , G06F13/00
CPC分类号： G06F5/065 , G06F13/4059
摘要： A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.
摘要翻译：一种提供在计算机系统中的第一总线和第二总线之间有效数据传输的桥接电路。桥接电路接收指示存储要求从第一总线传送到第二总线的数据段的存储位置的地址。获取电路从第一总线获取所请求的数据，并且在存储所请求的数据的存储器位置之后顺序地预取存储在存储单元中的一个或多个附加数据段。预取的数据段存储在缓冲器中，以便通过后续数据传输请求立即访问。响应于接收到对应于地址输入电路上的特定数据段的地址，供应电路将每个数据段从缓冲器传送到第二总线。

82. 发明授权

US06976115B2 Peer-to-peer bus segment bridging 有权
标题翻译：点对点公交线路桥接
公开(公告)号：US06976115B2
公开(公告)日：2005-12-13
申请号：US10112344
申请日：2002-03-28
申请人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
发明人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
IPC分类号： G06F3/00 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4031
摘要： A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
摘要翻译：描述了一种用于促进桥接总线段之间的对等通信的正确排序的方法和装置。根据本发明的一个实施例，当检测到连接在桥的同一侧上的分开的总线段上的设备之间的对等通信时，发出围栏命令。 fence命令插入到与总线段相对应的I / O集线器中的多个缓冲器中，以迫使临时排序I / O集线器的所有管道。一旦从该缓冲器读取了fence命令，则该中继器禁止处理来自缓冲器的后续命令，直到从多个缓冲器中的所有其他缓冲器读取相应的fence命令，从而确保对等通信的正确排序。

83. 发明授权

US06370624B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06370624B1
公开(公告)日：2002-04-09
申请号：US09712010
申请日：2000-11-13
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

84. 发明授权

US06199145B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06199145B1
公开(公告)日：2001-03-06
申请号：US09032434
申请日：1998-02-27
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

85. 发明授权

US6026455A Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system 失效
标题翻译：用于为重试总线主机向计算机系统中连接两条总线的数据传输桥提供有保障的访问的架构和方法
公开(公告)号：US6026455A
公开(公告)日：2000-02-15
申请号：US201817
申请日：1994-02-24
申请人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
发明人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
IPC分类号： G06F13/40 , G06F13/36
CPC分类号： G06F13/4031
摘要： A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
摘要翻译：适于与PCI和辅助总线电路相关联的桥接电路，桥接电路包括用于存储特定PCI总线主机尝试访问辅助总线并已被迫重试该接入的指示的电路，用于屏蔽的电路任何重试直到总线再次可用，以及用于提供间隔时间的电路，在该间隔期间，重试PCI总线主机被保证访问辅助总线，有利于在总线被放弃之后辅助总线上的总线主机，使得重试次序不会产生导致PCI总线带宽损失的操作。

86. 发明授权

US5666556A Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit 失效
标题翻译：用于重定向寄存器访问请求的方法和装置，其中寄存器集与中央处理单元分离
公开(公告)号：US5666556A
公开(公告)日：1997-09-09
申请号：US710572
申请日：1996-09-19
申请人： Narendra Khandekar , Jasmin Ajanovic
发明人： Narendra Khandekar , Jasmin Ajanovic
IPC分类号： G06F13/40 , G06F12/06
CPC分类号： G06F13/4027
摘要： A register address space is defined with a capacity large enough to accommodate substantial growth in the number of required registers. Unused register locations are reserved for future use. Access requests directed to reserved addresses are redirected to a physical register containing the same stored value that would be returned if a physical register were associated with the reserved address to which the access was originally directed. The physical register is separate from any central processing unit.
摘要翻译：寄存器地址空间被定义为具有足够大的容量以容纳所需寄存器的数量的显着增长。未使用的寄存器位置保留供将来使用。指向保留地址的访问请求被重定向到物理寄存器，该物理寄存器包含与物理寄存器与访问最初指向的保留地址相关联时返回的相同存储值。物理寄存器与任何中央处理单元分开。

87. 发明授权

US06516375B1 Peripheral component interconnect (PCI) configuration emulation for hub interface 有权
标题翻译：用于集线器接口的外围组件互连（PCI）配置仿真
公开(公告)号：US06516375B1
公开(公告)日：2003-02-04
申请号：US09433275
申请日：1999-11-03
申请人： Jasmin Ajanovic , David J. Harriman , Serafin E. Garcia
发明人： Jasmin Ajanovic , David J. Harriman , Serafin E. Garcia
IPC分类号： G06F1310
CPC分类号： G06F13/4027 , Y10S370/912
摘要： A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address formatted in accordance with a peripheral component interconnect (PCI) specification. The configuration access request packet is received from the hub interface by a second hub agent.
摘要翻译：配置接入请求分组从第一集线器代理发送到集线器接口。配置接入请求分组包括根据外围组件互连（PCI）规范格式化的地址。由第二集线器代理从集线器接口接收配置接入请求分组。

88. 发明授权

US06496895B1 Method and apparatus for intializing a hub interface 有权
标题翻译：用于初始化集线器接口的方法和装置
公开(公告)号：US06496895B1
公开(公告)日：2002-12-17
申请号：US09430996
申请日：1999-11-01
申请人： David J. Harriman , Jasmin Ajanovic
发明人： David J. Harriman , Jasmin Ajanovic
IPC分类号： G06F1300
CPC分类号： G06F13/387
摘要： A first control hub component, within a computer system, having a first logic to synchronize an internal clock generator of the first control hub with an external clock generator in response to the external clock generator transitioning to a high power state. In response to the internal clock generator being synchronized with the external clock generator, the first logic initiates the first control hub to transmit a request packet to a second control hub via an interface. The first logic monitors the interface for receipt of a completion packet in reply to the request packet, wherein in response to the completion packet the first control hub is operable to continue communication with the second hub via the interface.
摘要翻译：计算机系统内的第一控制集线器组件具有第一逻辑，用于响应于外部时钟发生器转换到高功率状态，将第一控制集线器的内部时钟发生器与外部时钟发生器同步。响应于与外部时钟发生器同步的内部时钟发生器，第一逻辑启动第一控制集线器以经由接口向第二控制集线器发送请求分组。第一逻辑监视接口以接收到响应于请求分组的完成分组，其中响应于完成分组，第一控制中心可操作以经由接口继续与第二集线器通信。

89. 发明授权

US06374317B1 Method and apparatus for initializing a computer interface 有权
标题翻译：用于初始化计算机接口的方法和装置
公开(公告)号：US06374317B1
公开(公告)日：2002-04-16
申请号：US09414377
申请日：1999-10-07
申请人： Jasmin Ajanovic , Serafin Garcia , David J. Harriman
发明人： Jasmin Ajanovic , Serafin Garcia , David J. Harriman
IPC分类号： G06F1310
CPC分类号： G06F13/4045
摘要： According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodiment, the first hub agent comprises a presence detect module and control logic coupled to the presence detect module. The control logic responds to a central processing unit (CPU) poll request if the second hub agent is detected and does not respond to the CPU if the first device is not detected.
摘要翻译：根据一个实施例，计算机系统包括耦合到第一集线器代理的第一集线器代理和集线器接口。第一集线器代理适于对集线器接口进行采样，以便在计算机系统启动时检测第二集线器代理的存在。在另一实施例中，第一集线器代理包括耦合到存在检测模块的存在检测模块和控制逻辑。如果检测到第二集线器代理，则控制逻辑响应中央处理单元（CPU）轮询请求，如果未检测到第一设备，则该控制逻辑不响应CPU。

90. 发明授权

US06260105B1 Memory controller with a plurality of memory address buses 失效
标题翻译：具有多个存储器地址总线的存储器控制器
公开(公告)号：US06260105B1
公开(公告)日：2001-07-10
申请号：US08954620
申请日：1997-10-20
申请人： Mike W. Williams , Jasmin Ajanovic , Joseph H. Salmon
发明人： Mike W. Williams , Jasmin Ajanovic , Joseph H. Salmon
IPC分类号： G06F1206
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A memory controller for a computer system includes a first memory address bus and a second memory, address bus. The memory controller further includes circuitry that toggles one of the first and second memory address buses at a time. Because only one memory address bus is toggled at once, the first and second memory address buses can share power and ground pins, thereby reducing the number of power and ground pins on the memory controller.
摘要翻译：用于计算机系统的存储器控制器包括第一存储器地址总线和第二存储器地址总线。存储器控制器还包括一次切换第一和第二存储器地址总线之一的电路。因为一次只切换一个存储器地址总线，所以第一和第二存储器地址总线可以共享电源和接地引脚，从而减少存储器控制器上的电源和接地引脚的数量。

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