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81. 发明授权

US5976984A Process of making unlanded vias 失效
标题翻译：制作无人化过孔的过程
公开(公告)号：US5976984A
公开(公告)日：1999-11-02
申请号：US1416
申请日：1997-12-30
申请人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
发明人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L23/522 , H01L21/02
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76829 , H01L2924/0002
摘要： A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.
摘要翻译：公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。

82. 发明授权

US5959361A Dielectric pattern 失效
标题翻译：电介质图案
公开(公告)号：US5959361A
公开(公告)日：1999-09-28
申请号：US59691
申请日：1998-04-14
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L51/00 , H01L21/321
CPC分类号： H01L21/76832 , H01L21/76804 , H01L21/7681 , H01L21/76811
摘要： A dielectric pattern. On a substrate having a metal wiring layer formed thereon, a first dielectric layer and a first masking layer are formed. A cap insulation layer is formed on the masking layer. The first dielectric layer, the first masking layer and the cap insulation layer are penetrated through by a first opening. A second dielectric layer and a second masking layer are formed on the cap insulation layer. The second dielectric layer and the second masking layer are penetrated through by a second opening. The first and the second openings are contiguous without intermittence.
摘要翻译：电介质图案。在其上形成有金属布线层的基板上，形成第一介电层和第一掩模层。在掩模层上形成盖绝缘层。第一介电层，第一掩模层和盖绝缘层穿过第一开口。第二介电层和第二掩模层形成在盖绝缘层上。第二介电层和第二掩蔽层穿过第二开口。第一和第二开口是连续的而不间断。

83. 发明授权

US5956598A Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit 有权
标题翻译：用于在集成电路中制造具有圆角的浅沟槽隔离结构的方法
公开(公告)号：US5956598A
公开(公告)日：1999-09-21
申请号：US164736
申请日：1998-10-01
申请人： Kuo-Tai Huang , Gwo-Shii Yang , Tri-Rung Yew , Water Lur
发明人： Kuo-Tai Huang , Gwo-Shii Yang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure with a rounded corner in integrated circuits through a rapid thermal process (RTP). In the fabrication of the STI structure, a sharp corner is often undesirably formed. This sharp corner , if not eliminated, causes the occurrence of a leakage current when the resultant IC device is in operation that significantly degrades the performance of the resultant IC device. To eliminate this sharp corner , an RTP is performed at a temperature of above 1,100.degree. C., which temperature is higher than the glass transition temperature of the substrate, for about 1 to 2 minutes. The result is that the surface of the substrate is oxidized into an sacrificial oxide layer and the sharp corner is deformed into a rounded shape with a larger convex radius of curvature. This allows the problems arising from the existence of the sharp corner to be substantially eliminated. Compared to the prior art, this method not only is more simplified in process, but also allows a considerable saving in thermal budget, which makes this method more cost-effective to implement than the prior art.
摘要翻译：提供半导体制造方法，用于通过快速热处理（RTP）在集成电路中制造具有圆角的浅沟槽隔离（STI）结构。在STI结构的制造中，通常不希望地形成尖锐的拐角。如果不消除这个尖角，则当所得到的IC器件运行时会导致泄漏电流的发生，这显着降低了所得IC器件的性能。为了消除这个尖角，RTP在高于1100℃的温度下进行，该温度高于基板的玻璃化转变温度约1至2分钟。其结果是，衬底的表面被氧化成牺牲氧化物层，并且尖角变形为具有较大凸曲率半径的圆形形状。这允许基本上消除由尖角存在引起的问题。与现有技术相比，该方法不仅在过程中更简化，而且还可以大大节省热预算，这使得该方法比现有技术更具成本效益。

84. 发明授权

US5801094A Dual damascene process 失效
标题翻译：双镶嵌工艺
公开(公告)号：US5801094A
公开(公告)日：1998-09-01
申请号：US873500
申请日：1997-06-12
申请人： Tri-Rung Yew , Meng-Chang Liu , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Meng-Chang Liu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/7681 , H01L21/76804
摘要： A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.
摘要翻译：双镶嵌工艺通过首先在器件结构上提供层间氧化物并用蚀刻停止层覆盖层间氧化物层，形成两层金属互连结构。蚀刻停止层被图案化以形成对应于将要形成在两层互连结构的第一层中的互连图案的开口。在蚀刻停止层被图案化之后，在蚀刻停止层上方提供金属间氧化物层。因为蚀刻停止层相对较薄，所以形成在金属间氧化物层的表面上的形貌相对较小。然后在金属间氧化物层之上提供光致抗蚀剂掩模，其中掩模中的开口在布线的图案中的金属间氧化物层的暴露部分中设置有互连结构的第二层。蚀刻金属间氧化物层，并且蚀刻工艺继续在层间氧化物中形成开口，其中层间氧化物被蚀刻停止层中的开口暴露。因此，在单个蚀刻步骤中，限定了用于二级布线和第一级互连的开口。然后将金属沉积在结构上，通过化学机械抛光除去多余的金属以限定两层互连结构。

85. 发明授权

US08609981B2 P-type transparent conductive oxide for solar cell comprising molybdenum trioxide doped with indium 有权
标题翻译：用于太阳能电池的P型透明导电氧化物，其包含掺杂有铟的三氧化钼
公开(公告)号：US08609981B2
公开(公告)日：2013-12-17
申请号：US13104744
申请日：2011-05-10
申请人： Han-Yi Chen , Chia-Hsiang Chen , Huan-Chieh Su , Kuo-Liang Liu , Tri-Rung Yew
发明人： Han-Yi Chen , Chia-Hsiang Chen , Huan-Chieh Su , Kuo-Liang Liu , Tri-Rung Yew
IPC分类号： H01L31/00 , H01B1/02 , H01B1/08
CPC分类号： H01B1/08 , B82Y30/00 , C01G39/02 , C01P2002/54 , C01P2004/16 , C01P2004/17 , C01P2006/40 , H01G9/2031 , H01G9/2059 , H01L31/022466 , H01L31/035227 , H01L31/03529 , H01L31/072 , H01L31/1884 , H01L51/442 , Y02E10/50
摘要： A p-type transparent conductive oxide and a solar cell containing the p-type transparent conducting oxide, wherein the p-type transparent conductive oxide includes a molybdenum trioxide doped with an element having less than six valence electrons, the element is selected from the group consisting of alkali metals, alkaline earth metals, group III elements, group IV, group V, transition elements and their combinations. Doping an element having less than six valence electron results in hole number increase, and thus increasing the hole drift velocity, and making Fermi level closer to the range of p-type materials. Hence, a p-type transparent conductive material is generated. This p-type transparent conducting oxide not only has high electron hole drift velocity, low resistivity, but also reaches a transmittance of 88% in the visible wavelength range, and therefore it is very suitable to be used in solar cells.
摘要翻译： p型透明导电氧化物和含有p型透明导电氧化物的太阳能电池，其中p型透明导电氧化物包括掺杂有少于6价电子的元素的三氧化钼，该元素选自由碱金属，碱土金属，III族元素，IV族，V族，过渡元素及其组合组成。掺杂具有小于6价电子的元素导致孔数增加，从而增加空穴漂移速度，并使费米能级更接近p型材料的范围。因此，产生p型透明导电材料。该p型透明导电氧化物不仅具有高的电子空穴漂移速度，低电阻率，而且在可见光波长范围内也达到88％的透射率，因此非常适用于太阳能电池。

86. 发明授权

US08368057B2 Organic thin film transistor 有权
标题翻译：有机薄膜晶体管
公开(公告)号：US08368057B2
公开(公告)日：2013-02-05
申请号：US12807620
申请日：2010-09-09
申请人： Yu-Ping Wang , Heng-Wen Ting , Chung-Min Tsai , Tri-Rung Yew
发明人： Yu-Ping Wang , Heng-Wen Ting , Chung-Min Tsai , Tri-Rung Yew
IPC分类号： H01L29/08 , H01L51/00
CPC分类号： H01L51/0053 , H01L51/0545
摘要： An organic thin film transistor includes: a gate electrode, a gate insulating film, a source electrode, a drain electrode, and an organic active layer. The organic active layer includes an organic semiconductor compound represented by the following formula (A) as defined in the specification.
摘要翻译：有机薄膜晶体管包括：栅极，栅极绝缘膜，源电极，漏电极和有机活性层。有机活性层包括由说明书中定义的下式（A）表示的有机半导体化合物。

87. 发明申请

US20090325370A1 Field-effect transistor structure and fabrication method thereof 审中-公开
标题翻译：场效应晶体管结构及其制造方法
公开(公告)号：US20090325370A1
公开(公告)日：2009-12-31
申请号：US12584401
申请日：2009-09-03
申请人： Tsung-Yeh Yang , Tri-Rung Yew
发明人： Tsung-Yeh Yang , Tri-Rung Yew
IPC分类号： H01L21/28
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0545
摘要： A field-effect transistor (FET) structure is provided. The FET structure includes a gate substrate, a dielectric layer, conductive electrodes, and a carbon nanotube (CNT). The gate substrate is made of a conductive material. The dielectric layer is disposed on the substrate. The conductive electrodes are disposed on the dielectric layer, and contain nickel and chromium. The CNT is disposed on the dielectric layer and electrically connects two conductive electrodes
摘要翻译：提供场效应晶体管（FET）结构。 FET结构包括栅极基板，电介质层，导电电极和碳纳米管（CNT）。栅极衬底由导电材料制成。电介质层设置在基板上。导电电极设置在电介质层上，并含有镍和铬。 CNT布置在电介质层上并电连接两个导电电极

88. 发明申请

US20090191616A1 Biosensor structure and fabricating method thereof 审中-公开
标题翻译：生物传感器结构及其制造方法
公开(公告)号：US20090191616A1
公开(公告)日：2009-07-30
申请号：US12231071
申请日：2008-08-27
申请人： Yi-Chun Lu , Tri-Rung Yew , Hwan-You Chang , Ya-Shuan Chuang
发明人： Yi-Chun Lu , Tri-Rung Yew , Hwan-You Chang , Ya-Shuan Chuang
IPC分类号： C12M1/00
CPC分类号： G01N33/48728
摘要： A biosensor structure and a method for fabricating the same are described. The biosensor structure for detecting at least a single cell includes a substrate with an insulating surface, a conductive layer and a plurality of capture molecules. The conductive layer is disposed on the substrate, and has a first pattern and a second pattern separated from each other. The first pattern includes a plurality of first finger configurations, and the second pattern includes a plurality of second finger configurations, so as to form interdigitated array. The capture molecules are immobilized on the conductive layer, such that the cell that is bound specifically to the capture molecules on two adjacent first and second finger configurations is detected. The biosensor structure is feasible for real-time (
摘要翻译：对生物传感器结构及其制造方法进行说明。用于检测至少单个电池的生物传感器结构包括具有绝缘表面的基板，导电层和多个捕获分子。导电层设置在基板上，并且具有彼此分离的第一图案和第二图案。第一图案包括多个第一手指配置，并且第二图案包括多个第二手指配置，以便形成相互指向的数组。捕获分子被固定在导电层上，使得在两个相邻的第一和第二手指配置上特异性结合捕获分子的细胞被检测。生物传感器结构对于单个细胞的实时（<3分钟），特异性和定量靶向细胞检测是可行的。

89. 发明申请

US20080067681A1 INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：互连结构及其制造方法
公开(公告)号：US20080067681A1
公开(公告)日：2008-03-20
申请号：US11756853
申请日：2007-06-01
申请人： Tzu-chun Tseng , Tri-Rung Yew , Chung-Min Tsai
发明人： Tzu-chun Tseng , Tri-Rung Yew , Chung-Min Tsai
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53276 , H01L21/28562 , H01L21/76849 , H01L21/76879 , H01L23/53238 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure is provided. The interconnection structure includes a substrate, a conductive barrier layer, a dielectric layer and a carbon nanotube. A conductive region is disposed in the substrate. The conductive barrier layer is disposed over the conductive region and the conductive barrier layer includes iron, cobalt or nickel. The dielectric layer is disposed on the substrate. The carbon nanotube is disposed in the dielectric layer to electrically connect with the conductive barrier layer.
摘要翻译：提供互连结构。互连结构包括基板，导电阻挡层，电介质层和碳纳米管。导电区域设置在基板中。导电阻挡层设置在导电区域之上，导电阻挡层包括铁，钴或镍。电介质层设置在基板上。碳纳米管设置在电介质层中以与导电阻挡层电连接。

90. 发明授权

US07067917B2 Gradient barrier layer for copper back-end-of-line technology 有权
标题翻译：用于铜后端技术的梯度屏障层
公开(公告)号：US07067917B2
公开(公告)日：2006-06-27
申请号：US10337292
申请日：2003-01-07
申请人： Fu-Tai Liou , Cheng-Yu Hung , Tri-Rung Yew
发明人： Fu-Tai Liou , Cheng-Yu Hung , Tri-Rung Yew
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , C23C14/027 , C23C14/0641 , C23C16/029 , C23C16/34 , H01L21/2855 , H01L21/28556 , H01L21/76805 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , Y10T428/26 , H01L2924/00
摘要： The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1−x/TaN/TaxN1−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films. After subsequent thermal cycle processes such as metal alloy, the inter-layer diffusion occurs and a more smooth distribution of Ta and N is achieved for the gradient barrier. The advantages of forming the gradient barrier include a well-controlled process, a strong adhesion between via and landing metal, more uniform step coverage, and less brittle to reduce crack.
摘要翻译：本发明涉及梯度阻挡层的结构。具有不同成分/金属的金属/金属盐的复合结构的梯度屏障，例如Ta / Ta x N 1-x / TaN / Ta x x 1 / x 1 / x 3/1 / x 2/1 / x 3 / 提出了替代传统的铜金属化屏障的方法。梯度屏障可以在化学气相沉积（CVD）工艺或多目标物理气相沉积（PVD）工艺中形成。对于CVD工艺，使用良好控制的反应气体注入特性，可以逐渐调节钽（Ta）和氮（N）的比例，形成梯度屏障。对于多目标PVD工艺，通过沉积多层不同组成的Ta x N 1 x-x膜形成梯度屏障。在随后的热循环过程如金属合金之后，发生层间扩散，并且对梯度屏障实现了更平稳的Ta和N分布。形成梯度屏障的优点包括良好控制的工艺，通孔和着陆金属之间的牢固粘附，更均匀的台阶覆盖，并且较不易碎以减少裂纹。

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