专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明专利

JPS53148935A STRUCTURE METHOD OF PLA 失效
公开(公告)号：JPS53148935A
公开(公告)日：1978-12-26
申请号：JP6332977
申请日：1977-06-01
申请人： HITACHI LTD
发明人： KIHARA TOSHIMASA , MATSUBARA KIYOSHI
IPC分类号： H03K19/177
摘要： PURPOSE:To decrease the occupied area of programmable logic array PLA by adding a circuit, which inhibits the output of the AND circuit by the output of other AND xircuit, to the output part of the AND circuit groups.

82. 发明专利

JPS53102642A DECIMAL COMPENSATING CIRCUIT FOR SUBTRACTION 失效
公开(公告)号：JPS53102642A
公开(公告)日：1978-09-07
申请号：JP1711577
申请日：1977-02-21
申请人： HITACHI LTD
发明人： MATSUBARA KIYOSHI , KIHARA TOSHIMASA , FUNABASHI TSUNEO
IPC分类号： G06F7/494 , G06F7/50 , G06F7/508
摘要： PURPOSE:To realize the decimal compensating instruction for subtraction with addition of minimal scale of hardware.

83. 发明专利

JP2503968B2 失效
公开(公告)号：JP2503968B2
公开(公告)日：1996-06-05
申请号：JP10696786
申请日：1986-05-10
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NAKAMURA HIDEO , HAGIWARA YOSHIMUNE , KIHARA TOSHIMASA , MATSUBARA KYOSHI , YAMAURA TADASHI
IPC分类号： G11C17/00 , G06F12/16 , G11C16/02 , G11C16/06

84. 发明专利

JPH021085A DATA INPUT DEVICE 失效
公开(公告)号：JPH021085A
公开(公告)日：1990-01-05
申请号：JP2980789
申请日：1989-02-10
申请人： HITACHI LTD
发明人： KIHARA TOSHIMASA
IPC分类号： G06F3/05 , G06F15/78
摘要： PURPOSE:To make an input pin into a multifunctional input pin and to miniaturize and LSI by inputting input signals to be discriminated by a desired threshold voltage to the same input pin and deciding and reading the input signals with two or more types of deciding values. CONSTITUTION:For a signal input external terminal IP, address switches S1-Sn are respectively connected between the output terminals of plural input buffers VTH1-VTHn having different threshold voltages with each other and data bus BUS in the LSI. For these switches S1-Sn, a desired switch out of them is switch- controlled according to the program of a microcomputer. For example, when a data signal to make a line l8 into H is outputted to an address bus ABUS, and next, a read control signal is supplied to a terminal W of a register RG, the data are read to the register RG, and a decoder circuit DEC decodes the read data and makes the line l8 into H. Thus, the switch is turned on, the signal, the level of which is discriminated by the desired threshold voltage, is transferred to the bus BUS and read to a memory, etc.

85. 发明专利

JPS63100522A CONTROL METHOD FOR CLOCK SIGNAL SUPPLY IN DATA PROCESSOR 失效
公开(公告)号：JPS63100522A
公开(公告)日：1988-05-02
申请号：JP21281287
申请日：1987-08-28
申请人： HITACHI LTD
发明人： MAEJIMA HIDEO , KATSURA AKIHIRO , KIHARA TOSHIMASA , AKAO YASUSHI
IPC分类号： G06F1/08 , G06F1/00 , G06F1/04 , G06F15/78
摘要： PURPOSE:To reduce power consumption by providing a clock inhibiting instruction and inhibiting supply of a clock signal of a logic circuit if this instruction is read out. CONSTITUTION:When a micro instruction for clock supply request is read out, a signal 3d is set to the high level. This state is stored in a flip flop 300 by a clock 3b, and a signal 3e obtained by this operation is synchronized with a flip flop 301 by a clock 3a. A signal 3f synchronized with the clock 3a sets a flip flop 302 by the clock 3b to indicate the clock stop. A clock stop signal 3g is synchronized with the clock 3a by a flip flop 303, and clock gates 304-306 are controlled by a pair of signals 3h and 3i (the inverse of 3h), and a clock 3x corresponding to the clock 3a is stopped in the high-level state by a gate 305, and clocks 3y and 3z corresponding to clocks 3b and 3c are stopped in the low-level state.

86. 发明专利

JPS6198443A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS6198443A
公开(公告)日：1986-05-16
申请号：JP21847984
申请日：1984-10-19
申请人： Hitachi Ltd
发明人： KIHARA TOSHIMASA
IPC分类号： G06F9/30 , G06F9/22 , G06F9/26 , G06F15/78
CPC分类号： G06F9/262
摘要： PURPOSE:To enable a control part to control directly an input/output port with no intervention of an executing unit, by providing newly an input/output port which is controlled directly by the control signal delivered from a micro- ROM into a microprocessor. CONSTITUTION:A microinstruction is stored in a micro-ROM11 for each address. The contents of an instruction register 12 are decoded by an address decoder 13 when a macroinstruction read out of a memory 5 is fetched by an instruction register 12 via a data bus 3. Then an access is given to the corresponding address in the ROM11, and a microinstruction is read out. The macroinstruction fetched by the register 12 is executed by reading out plural microinstructions out of the ROM11. Then the following microinstructions are read out successive ly according to the next address written to the next address field of the microinstruction given from the ROM11.
摘要翻译：目的：使控制部分能够直接控制输入/输出端口，而不需要执行单元的干预，通过提供新的直接由微ROM传送到微处理器的控制信号控制的输入/输出端口。规定：微指令存储在每个地址的micro-ROM11中。当通过数据总线3由指令寄存器12取出从存储器5读出的宏指令时，指令寄存器12的内容由地址解码器13解码。然后，访问ROM11中的相应地址，读出一个微指令。通过从ROM11中读出多个微指令来执行由寄存器12取出的宏指令。然后根据写入从ROM11给出的微指令的下一个地址字段的下一个地址连续读出以下微指令。

87. 发明专利

JPS6118171A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6118171A
公开(公告)日：1986-01-27
申请号：JP13717484
申请日：1984-07-04
申请人： Hitachi Ltd
发明人： MATSUBARA KIYOSHI , KIHARA TOSHIMASA
IPC分类号： H01L21/8238 , H01L21/8246 , H01L27/02 , H01L27/092 , H01L27/10 , H01L27/112 , H01L29/78
CPC分类号： H01L27/0266
摘要： PURPOSE:To simplify manufacturing process without decreasing electrostatic breakdown voltage, by employing a double diffused drain structure for a clamp MOS element in electrostatic protecting circuit as well as for the MOS element in an internal circuit. CONSTITUTION:A substrate 10 is provided with the MOS element in an internal circuit 20 and with an input diffused resistor and a clamp MOS element in an electrostatic protecting circuit 30. The high concentration of B is implanted in the internal circuit 20 which has a double diffused drain structure consisting of an N diffused layer 201 implanted with As and an N diffused layer 202 implanted with P. The electrostatic protecting circuit 30 has the double diffused drain structure consisting of N diffused layers 301 and 302 implanted with As and N diffused layers 303 and 304 implanted with P, in which the As and the P are implanted simultaneously. No photoresist process is required for providing a single diffused drain structure in the electrostatic protecting circuit. Thus, the manufacturing process can be simplified while the electrostatic breakdown voltage is improved.
摘要翻译：目的：为了简化制造过程而不降低静电击穿电压，通过在静电保护电路中使用双扩散漏极结构以及内部电路中的MOS元件。构成：衬底10在内部电路20中设置有MOS元件，并且在静电保护电路30中具有输入扩散电阻器和钳位MOS元件.B的高浓度注入内部电路20中，该内部电路20具有双由掺杂有As的N +扩散层201和注入P的N +扩散层202构成的扩散漏极结构。静电保护电路30具有由N +扩散层301和 302植入了植入了P的As和N +扩散层303和304，其中As和P被同时植入。在静电保护电路中提供单个扩散漏极结构不需要光致抗蚀剂工艺。因此，可以简化制造工艺，同时提高静电击穿电压。

88. 发明专利

JPS60237700A LOGICAL CIRCUIT 失效
公开(公告)号：JPS60237700A
公开(公告)日：1985-11-26
申请号：JP7090785
申请日：1985-04-05
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , SHIBUKAWA MASARU , KIHARA TOSHIMASA , MATSUBARA KIYOSHI
IPC分类号： G11C17/12 , G11C17/00 , H03K19/096 , H03K19/177
摘要： PURPOSE:To reduce electric power consumption and occupying area of a ROM circuit by supplying the decoder output from a NAND circuit via an inverter to the gates of the ROM cells of a NOR circuit so that the flow of through-current to the ROM cells is prevented. CONSTITUTION:The output from a decoder part 20 of the NAND circuit provided with N type FET01-0i for logical gates between P, N type FETs 21 and 22 for precharging and switching is supplied via the inverter 31 to the gates of the ROM cells of the N type FETs 311-3MN of the NOR circuit. The floating capacity between the FETs 21 and 01 of the output line of such decoder 20 is slight as compared with the floating capacity of the output lines 410-4N0 of the ROM. The FETs 311-3MN are turned off even if the FETs 21, 41-4N are simultaneously turned on and the flow of the through-current is thus prevented. As a result, the need for providing a transfer gate between the ROM cells and the ground is eliminated and the electric power consumption and occupying area of the ROM circuit are reduced.

89. 发明专利

JPS60227519A LOGIC CIRCUIT DEVICE 失效
公开(公告)号：JPS60227519A
公开(公告)日：1985-11-12
申请号：JP7090285
申请日：1985-04-05
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , SHIBUKAWA MASARU , KIHARA TOSHIMASA
IPC分类号： H03K19/096
摘要： PURPOSE:To constitute a logic circuit of an integrated circuit to operate the logic circuit starting from zero frequency, by providing a circuit which holds the output of the pre-stage logic circuit of two logic circuits during the period within which the 2nd clock is the logic level of the 1st clock between the two logic circuits which respectively operate at the 1st and 2nd clocks. CONSTITUTION:Both dynamic circuits 12 and 15 of the logic circuit device of a microcomputer are pre-charge operated at the timing of a clock CL2 from a clock generating circuit 10 and operated at the timing T1. Moreover, signals are slew by latches 13 and 16 at the timing T1 and input signals of the falling timing of the clock CL2 are held during the period of the timing T2. Furthermore, signals are made through by a latch 14 at the timing T2 and the output of the latch 13 is held at the rising timing of the clock CL2 during the period of the timing T1. The dynamic circuits 12 and 15 are operated at constant intervals and the pre-charge mode is set at the timing T2 at which the time width tends to be extended so as to operate the logic circuit device starting from a frequency which is close to the zero frequency.

90. 发明专利

JPS60217659A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60217659A
公开(公告)日：1985-10-31
申请号：JP7281284
申请日：1984-04-13
申请人： HITACHI LTD
发明人： SHIRASU TATSUMI , SUMINO YOSHIAKI , KIHARA TOSHIMASA , KEIDA HARUO
IPC分类号： H01L27/10 , H01L21/265 , H01L21/266 , H01L21/312
摘要： PURPOSE:To write a discriminating pattern only by adding a photo-resist process by forming a writing pattern and the discriminating pattern to the same mask and etching a film by using a mask for boring a discriminating pattern window, which can be used in common, immediately after the ion implantation of the writing pattern. CONSTITUTION:A photo-resist 13 is developed, the ions of an impurity, such as phosphorus, boron, etc. are implanted by using a writing pattern to form an ion implantation region 27, and the region 27 is annealed, thus controlling threshold voltage. A novel photo-resist 17 is applied under the state in which the photo- resist 13 is left. A window 18 in which a region, in which a discriminating pattern is shaped, is exposed is bored by using the photo-resist 17. When an SiO2 film 11 is etched by an etching liquid such as hydrofluoric acid and ammonium fluoride (1:6), the discriminating pattern 19 is shaped on the SiO2 film 11. Source- drain regions 20, 21, a polysilicon gate electrode 22, source-drain electrodes 23, 24, an inter-layer insulating film 25, etc. are formed through various processes.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式