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81. 发明专利

JPH05251727A 失效
公开(公告)号：JPH05251727A
公开(公告)日：1993-09-28
申请号：JP4653292
申请日：1992-03-04
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , USAMI MITSUO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI
IPC分类号： H01L31/10 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/90 , H04B10/02
摘要： PURPOSE:To obtain an optical communication system for preventing malfunction due to noise charge caused by alpha ray by transmitting optical signals such that the conditions can be satisfied by energy of the optical signals at the light-receiving section of a semiconductor light-receiving device. CONSTITUTION:The incident condition of alpha ray where the largest quantity of noise electric charge is generated is that when alpha rays pass through along a diagonal line 7 of a light-absorbing layer 2 of a light-receiving device, generated noise electric charge Qn is expressed by Formula II: when silicon is used as a material, the produced number of electron-hole pairs is about 50000 pairs/mum; when l=20mum, the is Qn=160fC, and the signal electric charge quantity Qs is expressed by Formula III. Conventionally, when noise electric charge due to alpha ray is not taken into account, Es is approximately 3fJ at transmitting rate 1Gb/s. For example, when u=0.8, Es=3fJ, nu=380THz (lambda=0.8mum), the signal electric charge quantity is Qs=1.5fC. In other works, when alpha rays strike the light receiving device, conventional Es causes a wrong operation. However, a wrong operation caused by noise electric charge can be prevented by setting optical signal energy Es of Formula I so that Qs is larger than Qn by taking into account the noise electric charge.

82. 发明专利

JPH05251663A 失效
公开(公告)号：JPH05251663A
公开(公告)日：1993-09-28
申请号：JP4823292
申请日：1992-03-05
申请人： HITACHI LTD
发明人： HIGUCHI HISAYUKI , TACHIBANA MASARU , UEHARA KEIJIRO , IDEI YOJI , TOYABE TATSU , WATANABE TOKUO
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE:To provide a title device which reduces alpha-ray soft errors, has a short writing speed, and is suitable for high speed action. CONSTITUTION:Feedbabck constant R1-R4 of a flip flop type memory cell are set short, while a memory node of the flip fop type memory cell is provided with a carrier emission circuit consisting of diodes D1, D2 of small storage time. Carriers generated by alpha-rays through this excess carrier emission circuits D1, D2 are filtered out in a very short time and alpha-ray information breakdown can be prevented if memory information is avoided from breakdown only for a time required to filter out carriers. Therefore, an increase in writing time accompanying feedback time constant, so that it can be applied for high speed memory devices with an improvement in anti-alpha-ray strength.

83. 发明专利

JPH05191264A SEMICONDUCTOR LOGIC CIRCUIT 失效
公开(公告)号：JPH05191264A
公开(公告)日：1993-07-30
申请号：JP275592
申请日：1992-01-10
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H03K19/003 , H03K19/086
摘要： PURPOSE:To make power consumption zero and to eliminate noise by forming the subject circuit with a current switch and an emitter follower comprising an npn bipolar transistor(TR) and a current switch and an emitter follower comprising a pnp bipolar TR. CONSTITUTION:Current switch sections CS1, CS2 are formed so that outputs change similarly. When an output of the CS1 is at an H level, an output of the CS2 is at an H level and when an output of the CS1 is at an L level, an output of the CS2 is at an L level. When an output of the CS1 is at an H level and an npn bipolar TR Q1 is turned on, an output of the CS2 is at an H level and a pnp bipolar Tr Q2 is turned off. Conversely when an output of the CS1 is at an L level and the npn bipolar TR Q1 is turned off, an output of the CS2 is at an L level and the pnp bipolar TR Q2 is turned on. Either of the bipolar TRs Q1, Q2 is turned off without fail independently of the output level of the CS1. No steady-state current flows in this case.

84. 发明专利

JPH0575438A COMPLEMENTARY EMITTER FOLLOWER 失效
公开(公告)号：JPH0575438A
公开(公告)日：1993-03-26
申请号：JP1591492
申请日：1992-01-31
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： HONMA NORIYUKI , NANBU HIROAKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： H03F3/50 , H03K17/04 , H03K17/62 , H03K19/086
摘要： PURPOSE:To provide an active pull-down circuit with low power consumption, at high speed and with high drive capability. CONSTITUTION:In the complementary emitter follower in which emitters of two bipolar transistors(TRs) Qn, Qp whose polarity differs from each other are connected and collectors of them are connected respectively to a relevant power supply, an input signal is inputted directly to the base of the one TR Qn and an input signal is inputted to the base of the other TR Qp via a capacitor and a current source Ib for a bias current is connected to the base of the TR Qp.

85. 发明专利

JPH0573407A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0573407A
公开(公告)日：1993-03-26
申请号：JP23147191
申请日：1991-09-11
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G06F12/06 , G06F12/08
摘要： PURPOSE:To miniaturize the semiconductor memory and to reduce its power consumption by mixing and storing data and an address in the same chip or the same memory macro. CONSTITUTION:When an index address IA is inputted to a memory, it passes through an input buffer IB1, is decoded by a decoder DEC1, and a cell in a cache memory cell array CMA is selected. Storage data of the selected cell is detected by a sense circuit S1, passes through an output buffer OB1 and is outputted as DATA to the outside of a chip. In parallel thereto, the index address IA passes through the input buffer IB1, is decoded by a decoder DEC2, and a cell in a table memory cell array IMA is selected. A tag address stored in the selected cell is detected by a sense circuit S2, compared with a tag address TA inputted from a CPU by a comparing circuit CMP, and its result is outputted as a HIT signal.

86. 发明专利

JPH04258021A SEMICONDUCTOR LOGIC CIRCUIT 失效
公开(公告)号：JPH04258021A
公开(公告)日：1992-09-14
申请号：JP1974891
申请日：1991-02-13
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： H03K19/08 , H03K19/086
摘要： PURPOSE:To reduce the power consumption by adding a FET whose drain connects to an output terminal and whose gate receives an inverse of an output signal and a bipolar Transistor(TR) whose base connects to a source of the FET to the semiconductor logic circuit. CONSTITUTION:A field effect TR (FET) M1 whose drain connects to an emitter of a bipolar TR Q3 outputting an output signal OUT and whose gate connects to a load element R2 and a bipolar TR Q4 whose base connects to a source of the TR M1, whose collector connects to the emitter of the TR Q3, and whose emitter connects to a voltage source VT are provided to the semiconductor logic circuit. The TR Q4 supplies a discharge current to an output signal line similarly to the case with a current source 12. Since the FETM1 turns on the TR Q4 only when the output signal changes from an H level to an L level, the discharge current flows only at a required time.

87. 发明专利

JPH0421995A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0421995A
公开(公告)日：1992-01-24
申请号：JP12407490
申请日：1990-05-16
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/414 , G11C11/412
摘要： PURPOSE:To accelerate time for inverting a cell and for writing by setting a potential VB of a bit line to impressing voltages VC and VE of the memory cell to be VB

88. 发明专利

JPH03268297A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH03268297A
公开(公告)日：1991-11-28
申请号：JP6424490
申请日：1990-03-16
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , SAKURAI YOSHIAKI
IPC分类号： G11C11/416
摘要： PURPOSE:To prevent the decrease of the degree of a margin of the operation of a memory due to the variation of an element characteristic by connecting a constant current circuit to a common contact to which the sources of MOS transistors whose drains are connected to the emitters of a pair of bipolar transistors are connected. CONSTITUTION:The sources of the MOS transistors (Tr) MNCS1, MNCS2 are connected in common, and a constant current source ISA is connected to this common contact. The function of the Trs MNS1, MNS2 are limited to the function as a switching means, and the driving current of a differential amplification circuit is determined by the constant current source ISA. Thus, even if the characteristic of the MOS Tr varies, the driving current of the differential amplification circuit can be kept constant, and the decrease of the margin of operation due to the variation of the characteristic of the MOS Tr can be prevented.

89. 发明专利

JPH03152798A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPH03152798A
公开(公告)日：1991-06-28
申请号：JP29213389
申请日：1989-11-09
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/413 , G11C11/414 , G11C11/417
摘要： PURPOSE:To dispense with a level conversion circuit and to accelerate a memory in which an ECL circuit and a MOS or BiMOS circuit are mixed by setting a source voltage to be applied to the MOS or BiMOS circuit at a value smaller than that to be applied to the ECL circuit. CONSTITUTION:The source voltages VDD, VSS to be applied to the MOS or BiMOS circuit 16 are set at the values smaller than the source voltages VCC, VEE to be applied to the ECL circuits 11-15. In other words, the potential of a power source line to which the ECL circuits 11-15 are connected is set at VCC and VEE, while, the potential of the power source line to which the MOS circuit 16 is connected is set at VDD and VSS different from VCC and VEE. Therefore, it is possible to conform the signal voltages of the ECL circuits 11-15 with that of the MOS circuit 16 by setting the source voltage to be applied to the ECL circuits 11-15 differently from that to be applied to the MOS circuit 16. In such a way, since no level conversion circuit is required, the operation of the memory in which the ECL circuit and the MOS or BiMOS circuit are mixed, etc., can be accelerated by the delay time of the level conversion circuit.

90. 发明专利

JPH03132995A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH03132995A
公开(公告)日：1991-06-06
申请号：JP26914589
申请日：1989-10-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , SAKURAI YOSHIAKI
IPC分类号： G11C11/417 , G11C11/414
摘要： PURPOSE:To make an input signal amplitude to be equal or less than an output signal amplitude by impressing an input signal through a level shift circuit to a second control circuit which controls a transistor, and setting the power supply potential of the second control circuit to be a smaller value than a first control circuit. CONSTITUTION:The power supply potential VS of a circuit consisting of a bipolar transistor Q1 which executes the charging of a load capacitance CL and MOS transistors MP1, MN1 which control its base potential, and the power supply potential VS' of a circuit consisting of a bipolar transistor Q2 which executes the electrical discharge of the load capacitance CL and MOS transistors MN2, MN3 which control its base potential, are set at different potentials. That is, VS' is set to be smaller than VS. And, the input signal supplied to the circuit which executes the discharge is given through a level shift circuit which consists of bipolar transistors Q3, Q4, and diodes D1, D2. Thus, the input signal amplitude can be made equal or less than the output signal amplitude.

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