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81. 发明授权

US6010941A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US6010941A
公开(公告)日：2000-01-04
申请号：US112629
申请日：1998-07-09
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.
摘要翻译：形成层叠容器电容器的半导体处理方法包括：a）相对于衬底提供一对隔开的导电流道，所述导电流道分别具有电绝缘侧壁间隔件和电绝缘帽，所述帽具有相应的外表面; b）在要与电容器进行电连接的流道之间提供节点; c）提供与所述节点电连接的导电柱，所述柱相对于所述流道之间的节点向外突出，并且具有位于两个流道盖之外的第一外表面，所述柱完全填充所述一对流道之间的空间，支柱所在的位置; d）在盖和导电柱之外提供绝缘介电层; e）蚀刻通过所述绝缘介电层的容器开口以向外暴露所述导电柱第一外表面; f）蚀刻暴露的导电柱以限定比第一外表面更靠近节点的支柱第二外表面并加深容器开口; g）在第二外导电柱表面之上的容器开口内提供导电存储节点容器层; h）在所述电容器存储节点层上提供电容器介电层; 以及i）在所述电容器介电层上方提供导电的外部电容器板。还公开了这种电容器结构。

82. 发明授权

US5821140A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
公开(公告)号：US5821140A
公开(公告)日：1998-10-13
申请号：US732067
申请日：1996-10-16
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.

83. 发明授权

US5786250A Method of making a capacitor 失效
标题翻译：制作电容器的方法
公开(公告)号：US5786250A
公开(公告)日：1998-07-28
申请号：US818597
申请日：1997-03-14
申请人： Zhiqiang Wu , Li Li , Kunal Parekh
发明人： Zhiqiang Wu , Li Li , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method of the present invention forms a vertically oriented structure connected with a source/drain region through an open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad. A dry etching process is used to remove a segment of the conductive layer formed over the volume of insulating material upon the landing pad, after which the volume of insulating material upon the landing pad is removed. Remaining is a storage node made upon of a continuous layer of conductive material that lines the recess and the open space. A dielectric layer and a cell plate are in one embodiment formed over the continuous layer of conducting material so as to extend down into the open space, thus completing a container capacitor.
摘要翻译：本发明的方法形成了通过开放空间与源极/漏极区域连接的垂直取向结构。在其中形成电容器存储节点的方法的一个实施例中，开放空间位于MOS DRAM存储器电路中的两个字线栅极叠层之间。薄的着陆板由导电材料形成，该导电材料在延伸到源极/漏极区域以及栅极堆叠顶部的开放空间中。绝缘层形成在栅极叠层和着陆焊盘上。通过绝缘层向下蚀刻凹陷以暴露着陆垫的环形部分。绝缘材料的体积留在开放空间中的着陆垫上。导电层沉积在与着陆焊盘暴露的环形部分接触的凹部中。使用干蚀刻工艺去除在着陆焊盘上形成在绝缘材料体积上的导电层的段，之后移除着陆焊盘上的绝缘材料的体积。剩余的是由连续的导电材料层制成的存储节点，其导引凹槽和开放空间。在一个实施例中，在导电材料的连续层上形成电介质层和电池板，以便向下延伸到开放空间中，从而完成容器电容器。

84. 发明授权

US5563089A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
标题翻译：在存储器单元的电容器阵列上形成位线的方法以及存储器单元的电容器阵列上的位线阵列
公开(公告)号：US5563089A
公开(公告)日：1996-10-08
申请号：US394545
申请日：1995-02-22
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; e）有点线 f）位于所述位线和所述有效区域之间的介电绝缘层; g）延伸穿过绝缘层并将位线与另一有源区域电互连的位线插头，位线插头包括导电环形环。还公开了利用环形互连环的集成电路，超越了存储器件。还公开了具有另外的径向向内的绝缘环形环和导电环的这种结构。还公开了一种在具有这种环的存储器单元的电容器阵列上形成位线的方法。

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