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81. 发明授权

US07432212B2 Methods of processing a semiconductor substrate 失效
标题翻译：处理半导体衬底的方法
公开(公告)号：US07432212B2
公开(公告)日：2008-10-07
申请号：US11490807
申请日：2006-07-20
申请人： Jeffrey W. Honeycutt , Gurtej S. Sandhu
发明人： Jeffrey W. Honeycutt , Gurtej S. Sandhu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0334
摘要： The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.
摘要翻译：本发明包括处理半导体衬底的方法。在一个实施方式中，提供了具有外表面的半导体衬底。这种表面具有围绕半导体衬底的周边边缘接收的周边区域。包含无定形碳的层设置在衬底外表面上。掩模层设置在无定形含碳层的外侧。抗蚀剂层设置在掩模层的外侧。外表面的周边区域的至少一部分包括无定形含碳层和抗蚀剂层，但基本上不含掩模层。使用抗蚀剂层和掩模层对无定形含碳层进行图案化，以有效地在半导体衬底上形成掩模。在图案化之后，半导体衬底通过掩模中形成的开口在掩模的内部进行处理。

82. 发明申请

US20080241386A1 Atomic Layer Deposition Methods 审中-公开
标题翻译：原子层沉积方法
公开(公告)号：US20080241386A1
公开(公告)日：2008-10-02
申请号：US12115412
申请日：2008-05-05
申请人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
发明人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
IPC分类号： C23C16/08
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
摘要翻译：本发明包括在基板上形成沉积的组合物层的原子层沉积方法。该方法包括将半导体衬底定位在原子层沉积室内。在基材上形成中间体组合物单层，随后是与中间体组合物反应所需的沉积组合物，共同地将多个不同的组合物沉积前体流入沉积室内的基底。材料粘附到室内部件表面，从而依次形成。在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。在反应气体流动之后，重复这种顺序形成。考虑进一步的实现。

83. 发明授权

US07402489B2 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same 有权
标题翻译：与具有低接触电阻层的高介电常数材料兼容的电容器及其形成方法
公开(公告)号：US07402489B2
公开(公告)日：2008-07-22
申请号：US11216415
申请日：2005-08-30
申请人： Gurtej S. Sandhu , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Pierre C. Fazan
IPC分类号： H01L21/8242
CPC分类号： H01L21/7687 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76895 , H01L27/10852 , H01L27/10855 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.
摘要翻译：一种存储单元电容器和用于形成具有存储节点电极的存储单元电容器的方法，所述存储节点电极包括介于导电插塞和抗氧化层之间的阻挡层。制造一层硅化钛以位于导电塞和抗氧化层之间。绝缘层在具有高介电常数的介电层的沉积和退火期间保护阻挡层的侧壁。

84. 发明授权

US07396720B2 High coupling memory cell 有权
标题翻译：高耦合存储单元
公开(公告)号：US07396720B2
公开(公告)日：2008-07-08
申请号：US10899913
申请日：2004-07-27
申请人： Sukesh Sandhu , Gurtej S. Sandhu
发明人： Sukesh Sandhu , Gurtej S. Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7881
摘要： A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.
摘要翻译：第一电介质层形成在衬底上。用作浮栅的单层第一导电层形成在第一介电层上。在第一导电层中形成槽，以增加浮栅与控制栅的电容耦合。在浮栅层上形成隔间介电层。在第二介电层上形成第二导电层以用作控制栅极。

85. 发明申请

US20080121976A1 Non-volatile memory cell devices and methods 有权
标题翻译：非易失性存储单元器件及方法
公开(公告)号：US20080121976A1
公开(公告)日：2008-05-29
申请号：US11513933
申请日：2006-08-31
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L29/788 , H01L21/04 , H01L29/68 , G11C11/34
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332
摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer.
摘要翻译：一种制造存储单元的方法，包括在第一介电层上形成纳米点并在纳米点上形成隔间电介质层，其中隔间电介质层封装在纳米点上。为了形成存储器单元的侧壁，隔离介电层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对栅极间电介质层选择性的蚀刻来去除间隔栅电介质层和纳米点的剩余部分。

86. 发明授权

US07368399B2 Methods of forming patterned photoresist layers over semiconductor substrates 有权
标题翻译：在半导体衬底上形成图案化光致抗蚀剂层的方法
公开(公告)号：US07368399B2
公开(公告)日：2008-05-06
申请号：US11477287
申请日：2006-06-28
申请人： Guy T. Blalock , Gurtej S. Sandhu , Jon P. Daley
发明人： Guy T. Blalock , Gurtej S. Sandhu , Jon P. Daley
IPC分类号： H01L21/31
CPC分类号： G03F7/091 , H01L21/0276
摘要： This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the fluid therein. The positive photoresist is patterned and developed to form a patterned photoresist layer, with the fluid within the pores being effective to reduce photoresist footing in the patterned photoresist layer than would otherwise occur in the absence of the fluid within the pores. Other aspects and implementations are contemplated.
摘要翻译：本发明包括在半导体衬底上形成图案化光致抗蚀剂层的方法。在一个实施方案中，在半导体衬底上形成多孔抗反射涂层。在多孔抗反射涂层的孔内提供光致抗蚀剂页脚还原液。在其中具有流体的多孔抗反射涂层上形成正性光致抗蚀剂。正性光致抗蚀剂被图案化和显影以形成图案化的光致抗蚀剂层，孔内的流体有效地减少图案化光致抗蚀剂层中的光致抗蚀剂底脚，而不是在孔内不存在流体的情况下发生的。考虑了其他方面和实现。

87. 发明授权

US07354812B2 Multiple-depth STI trenches in integrated circuit fabrication 有权
标题翻译：集成电路制造中的多深STI沟槽
公开(公告)号：US07354812B2
公开(公告)日：2008-04-08
申请号：US10931946
申请日：2004-09-01
申请人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/8249 , H01L21/336 , H01L21/331 , H01L21/76 , H01L33/00 , H01L29/76 , H01L31/00 , H01L29/00
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译：集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

88. 发明授权

US07352023B2 Constructions comprising hafnium oxide 有权
标题翻译：包含氧化铪的构造
公开(公告)号：US07352023B2
公开(公告)日：2008-04-01
申请号：US11485592
申请日：2006-07-11
申请人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
发明人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/1272 , H01L21/31645 , H01L27/10852 , H01L28/60 , H01L28/65 , H01L28/90 , H01L28/91 , H01L29/7833
摘要： The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.
摘要翻译：本发明包括形成含铪材料的方法，例如氧化铪。在一个方面，提供了半导体衬底，并且利用第一反应条件来形成在衬底上所需的结晶相和取向的含铪种子材料。随后，利用第二反应条件在种子材料上生长第二含铪材料。第二含铪材料处于与含铪种子材料的结晶相和取向不同的结晶相和/或取向。第二含铪材料可以是例如非晶相。然后将种子材料用于在第二含铪材料中诱导所需的结晶相和取向。本发明还包括使用含铪材料的电容器结构和包括电容器结构的电路组件。

89. 发明授权

US07344975B2 Method to reduce charge buildup during high aspect ratio contact etch 有权
标题翻译：在高纵横比接触蚀刻期间减少电荷积累的方法
公开(公告)号：US07344975B2
公开(公告)日：2008-03-18
申请号：US11213283
申请日：2005-08-26
申请人： Gurtej S. Sandhu , Max F. Hineman , Daniel A. Steckert , Jingyi Bai , Shane J. Trapp , Tony Schrock
发明人： Gurtej S. Sandhu , Max F. Hineman , Daniel A. Steckert , Jingyi Bai , Shane J. Trapp , Tony Schrock
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31116 , Y10S438/906
摘要： A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.
摘要翻译：描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。氧化物层沉积在下面的衬底上。由碳源气体形成等离子体蚀刻气体。掺杂剂混入气体中。掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。蚀刻停止在下面的基底。

90. 发明授权

US07344948B2 Methods of forming transistors 有权
标题翻译：形成晶体管的方法
公开(公告)号：US07344948B2
公开(公告)日：2008-03-18
申请号：US10050347
申请日：2002-01-15
申请人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
发明人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
IPC分类号： H01L21/4763
CPC分类号： H01L21/02332 , H01L21/0234 , H01L21/265 , H01L21/28061 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.
摘要翻译：本发明包括将氮掺入含氧化硅的层中的方法。将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。氮气随后在层内热退火以将至少一些氮与硅结合在层内。本发明还包括形成晶体管的方法。在半导体衬底上形成栅氧化层。栅氧化层包括二氧化硅。将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。随后，层内的氮被热退火以将至少大部分氮与硅结合。在栅极氧化物层上形成至少一个导电层。源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。本发明还包括晶体管结构。

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