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81. 发明授权

US06873088B2 Vibratory beam electromechanical resonator 有权
标题翻译：振动束机电谐振器
公开(公告)号：US06873088B2
公开(公告)日：2005-03-29
申请号：US10113789
申请日：2002-04-01
申请人： Thomas Skotnicki , Didier Dutartre , Pascal Ribot
发明人： Thomas Skotnicki , Didier Dutartre , Pascal Ribot
IPC分类号： H03H3/00 , H03H9/24 , H01L21/00 , H01L29/82
CPC分类号： H03H3/00 , H03H9/24
摘要： A resonator formed by the steps of defining an active single-crystal silicon layer delimited by a buried insulator layer, depositing a silicon-germanium layer by a selective epitaxy method so that the silicon-germanium layer grows above the active single-crystal silicon area, depositing by a non-selective epitaxy method a silicon layer and etching it according to a desired contour, and removing the silicon-germanium by a selective etching with respect to the silicon and to the insulator.
摘要翻译：一种由以下步骤形成的谐振器，所述谐振器通过限定由掩埋绝缘体层限定的有源单晶硅层，通过选择性外延法沉积硅 - 锗层，使得硅 - 锗层生长在活性单晶硅区域之上，通过非选择性外延法沉积硅层并根据期望的轮廓对其进行蚀刻，并通过相对于硅和绝缘体的选择性蚀刻去除硅锗。

82. 发明授权

US06746923B2 Method of fabricating a vertical quadruple conduction channel insulated gate transistor 有权
标题翻译：制造垂直四通导通绝缘栅晶体管的方法
公开(公告)号：US06746923B2
公开(公告)日：2004-06-08
申请号：US10114672
申请日：2002-04-02
申请人： Thomas Skotnicki , Emmanuel Josse
发明人： Thomas Skotnicki , Emmanuel Josse
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/165 , H01L29/7827
摘要： The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.
摘要翻译：垂直绝缘栅晶体管包括在半导体衬底上的垂直柱，其顶部包括源极和漏极区中的一个，位于柱的侧面和衬底顶表面上的栅极电介质层，以及半导体门静置在栅介质层上。源极和漏极区域中的另一个位于柱PIL的底部，并且绝缘栅极包括搁置在柱的侧面上的隔离的外部部分15和位于源极和漏极区域之间的柱内的隔离的内部部分14 。隔离的内部部分通过在源极和漏极区域之间延伸的两个连接半导体区域PL1，PL2从隔离的外部部分侧向分离，并形成两个非常细的柱。

83. 发明授权

US06656782B2 Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor 有权
标题翻译：用于制造具有绝缘体基板类型的结构的隔离栅晶体管的工艺以及相应的晶体管
公开(公告)号：US06656782B2
公开(公告)日：2003-12-02
申请号：US10084255
申请日：2002-02-27
申请人： Thomas Skotnicki , Stéphane Monfray , Alexandre Villaret
发明人： Thomas Skotnicki , Stéphane Monfray , Alexandre Villaret
IPC分类号： H01L218238
CPC分类号： H01L29/66651 , H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76289 , H01L29/66772
摘要： The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.
摘要翻译：源极，漏极和沟道区域在硅层中产生，其通过绝缘层与载体衬底垂直地完全隔离，并且通过浅沟槽类型的横向隔离区域横向限定。

84. 发明授权

US06555482B2 Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor 有权
标题翻译：用于制造具有两个栅极的MOS晶体管的工艺，其中一个栅极被埋入并且对应的晶体管
公开(公告)号：US06555482B2
公开(公告)日：2003-04-29
申请号：US09812717
申请日：2001-03-20
申请人： Thomas Skotnicki , Malgorzata Jurczak , Michel Haond
发明人： Thomas Skotnicki , Malgorzata Jurczak , Michel Haond
IPC分类号： H01L21302
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.
摘要翻译：制造MOS晶体管的方法包括在绝缘体上硅衬底内形成第一栅极，形成横向覆盖第一栅极的半导体沟道区，以及在沟道区的每一侧上形成半导体漏极和源极区。半导体沟道区域和漏极和源极区域可以通过在第一栅极的上表面上外延生长。通道区域可以通过在通道区域下形成隧道并且用第一电介质至少部分地填充隧道而与第一栅极的上表面隔离。第二栅极形成在沟道区域上并且横向于沟道区域。第二栅极可以通过第二电介质与沟道区的上表面分离。

85. 发明授权

US06507091B1 Transistor with indium-implanted SiGe alloy and processes for fabricating the same 失效
标题翻译：具有铟注入SiGe合金的晶体管及其制造方法
公开(公告)号：US06507091B1
公开(公告)日：2003-01-14
申请号：US09515787
申请日：2000-02-29
申请人： Thomas Skotnicki , Jérôme Alieu
发明人： Thomas Skotnicki , Jérôme Alieu
IPC分类号： H01L310328
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/76224 , H01L29/1054
摘要： An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided. Germanium is implanted into at least one region of a silicon substrate where a channel region of a transistor is to be formed, in order to form a buried layer of an Si1−xGex alloy in which 10−5≦x≦4×10−1. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer.
摘要翻译：提供了一种注入铟的晶体管。晶体管具有硅沟道区，其包括其中注入铟的Si1-xGex合金的掩埋层，其中10-5≤x≤4×10-1。还提供了用于制造铟注入晶体管的第一种方法。在硅衬底的表面的至少一个区域上制造多层复合膜，其中要形成晶体管的沟道区。该多层复合膜包括至少一个Si1-xGex合金层，其中10-5 <= x <= 4×10-1，以及外部硅层。将铟注入到Si1-xGex合金层中，并完成晶体管的制造，以便制造具有包含掩埋的Si1-xGex合金层的沟道区的晶体管。另外，提供了用于制造铟注入晶体管的第二种方法。将锗注入到要形成晶体管的沟道区的硅衬底的至少一个区域中，以形成Si1-xGex合金的掩埋层，其中10-5≤x≤4×10-1 。将铟注入到Si1-xGex合金层中，并完成晶体管的制造，以便制造具有包含掩埋的Si1-xGex合金层的沟道区的晶体管。

86. 发明授权

US06495403B1 Gate-all-around semiconductor device and process for fabricating the same 有权
标题翻译：全栅半导体器件及其制造方法
公开(公告)号：US06495403B1
公开(公告)日：2002-12-17
申请号：US09680035
申请日：2000-10-05
申请人： Thomas Skotnicki , Malgorzata Jurczak
发明人： Thomas Skotnicki , Malgorzata Jurczak
IPC分类号： H01L2184
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/6675 , H01L29/78648
摘要： A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface. A thin layer of a dielectric material that does not fill the tunnel is formed on the external and internal surfaces of the bridge structure and on the side walls. A conducting material is deposited so as to cover the bridge structure and fill the tunnel, and the conducting material is masked and etched in order to form a gate-all-around region for the semiconductor device. Also provided is a semiconductor device having a gate-all-around architecture.
摘要翻译：提供了一种用于制造具有栅极全能结构的半导体器件的方法。制造基板以包括活性中心区域，活性主表面被具有绝缘主表面的绝缘外围区域包围。活性主表面和绝缘主表面共同延伸并构成基材的主表面。在活性主表面上形成第一层Ge或SiGe合金，并且在第一层和绝缘主表面上形成硅层。掩模和蚀刻硅层和第一层，以便在活性主表面上形成堆叠，并且去除第一层，使得堆叠的硅层在活性主表面上形成桥结构。桥结构定义了具有活动主表面的对应部分的隧道。在桥结构的外表面和内表面上以及在侧壁上形成不填充隧道的介电材料的薄层。沉积导电材料以覆盖桥结构并填充隧道，并且对导电材料进行掩模和蚀刻，以形成半导体器件的栅极全周区域。还提供了具有栅极全能结构的半导体器件。

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