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81. 发明授权

US07135906B2 Delay circuit and delay synchronization loop device 有权
标题翻译：延迟电路和延迟同步环路装置
公开(公告)号：US07135906B2
公开(公告)日：2006-11-14
申请号：US10901220
申请日：2004-07-29
申请人： Yasuhiro Takai , Shotaro Kobayashi
发明人： Yasuhiro Takai , Shotaro Kobayashi
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00058 , H03K2005/00241 , H03K2005/00247 , H03K2005/00273 , H03L7/0814 , H03L7/087
摘要： A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.
摘要翻译：延迟电路包括具有多级延迟单元的第一延迟线电路，具有多级延迟单元的第二延迟线电路，与第一延迟单元的延迟单元的相应级相关联地设置的多个传输电路延迟线电路，所述传送电路控制第一延迟线电路的延迟单元的输出到第二延迟线电路的延迟单元的相关级的传送。第一延迟线电路各级的延迟单元反相输入信号。第二延迟线电路的各级延迟单元包括接收与所讨论的延迟单元相关联的传送电路的输出信号的逻辑电路和将前一级的输出信号发送到后级的输出信号。通过独立地选择输入信号的上升沿和下降沿的传播路径，使占空比变化。

82. 发明授权

US07071960B2 Image forming apparatus 失效
标题翻译：图像形成装置
公开(公告)号：US07071960B2
公开(公告)日：2006-07-04
申请号：US10808330
申请日：2004-03-25
申请人： Kiyoshi Toizumi , Taisuke Kamimura , Toshimitsu Gotoh , Tsutomu Yoshimoto , Yasuhiro Takai
发明人： Kiyoshi Toizumi , Taisuke Kamimura , Toshimitsu Gotoh , Tsutomu Yoshimoto , Yasuhiro Takai
IPC分类号： G03G15/24 , G03G15/045 , G03G15/047 , G03G15/05
CPC分类号： G03G15/05
摘要： Electron generating devices and LED arrays are arranged in a surrounding area of a photosensitive drum. The electron generating devices are located downstream of a cleaner and upstream of a developing unit with respect to a turning direction of the photosensitive drum with a specific gap between the electron generating devices and a surface of the photosensitive drum. The LED arrays are disposed against outer ends of the electron generating devices opposite to inner ends thereof facing the photosensitive drum. When activated by a driving circuit according to image information, individual LED elements of the LED arrays emit light, causing the electron generating devices to emit electrons in a pattern corresponding to the image information. The electrons emitted from the electron generating devices produce more electrons due to an electron avalanche phenomenon before reaching the photosensitive drum, eventually forming an electrostatic latent image on the surface of the photosensitive drum.
摘要翻译：电子发生器件和LED阵列布置在感光鼓的周围区域中。电子产生装置相对于感光鼓的转动方向位于清洁器的下游和显影单元的上游，在电子产生装置和感光鼓的表面之间具有特定的间隙。 LED阵列设置在电子产生装置的与端对着感光鼓的内端相对的外端。当根据图像信息被驱动电路激活时，LED阵列的各个LED元件发光，使得电子发生器件以对应于图像信息的图案发射电子。从电子产生装置发射的电子在到达感光鼓之前由于电子雪崩现象而产生更多的电子，最终在感光鼓的表面上形成静电潜像。

83. 发明申请

US20050236758A1 Paper feeder 有权
标题翻译：送纸器
公开(公告)号：US20050236758A1
公开(公告)日：2005-10-27
申请号：US11114081
申请日：2005-04-26
申请人： Toshiki Ohgita , Jinichi Nagata , Naofumi Okada , Kouzou Yamaguchi , Hideo Yoshikawa , Yasuhiro Takai , Syouichirou Yoshiura , Tsutomu Yoshimoto
发明人： Toshiki Ohgita , Jinichi Nagata , Naofumi Okada , Kouzou Yamaguchi , Hideo Yoshikawa , Yasuhiro Takai , Syouichirou Yoshiura , Tsutomu Yoshimoto
IPC分类号： B65H3/44 , B65H5/00
CPC分类号： B65H83/025 , B65H3/44 , B65H2402/10 , B65H2405/3311 , B65H2511/20 , B65H2220/02
摘要： A paper feeder includes a storage section, a feed path, a delivery section, and a receiving section. The storage section is configured to store therein plural sheet members to be fed to a processing apparatus which is operative to perform processing on the sheet members. The feed path allows each of the plural sheet members fed from the storage section to pass therethrough in a feed direction toward the processing apparatus. The delivery section is located most downstream on the feed path in the feed direction. The feed path is open to exterior in the delivery section. The receiving section is located upstream of the feed path in the feed direction for communication with a delivery section of a separate paper feeder having an identical construction with the present paper feeder when the separate paper feeder is disposed upstream of the present paper feeder in the feed direction.
摘要翻译：供纸器包括存储部分，馈送路径，传送部分和接收部分。存储部被配置为在其中存储要供给到可对片材部件进行处理的处理装置的多个片状部件。进给路径允许从存储部分供给的多个片状构件中的每一个在馈送方向上朝向处理装置通过。输送部分位于馈送方向上最靠近馈送路径的下游。进料路径在输送段内向外开放。接收部分在馈送方向上位于馈送路径的上游，以便当分离的供纸器设置在馈送器的上游时，与当前供纸器具有相同结构的单独的供纸器的传送部分连通方向。

84. 发明授权

US06674314B2 Interpolating circuit, DLL circuit and semiconductor integrated circuit 有权
标题翻译：内插电路，DLL电路和半导体集成电路
公开(公告)号：US06674314B2
公开(公告)日：2004-01-06
申请号：US10241986
申请日：2002-09-12
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： H03L706
CPC分类号： H03K5/131 , H03K5/133 , H03K5/15046 , H03L7/0814 , H03L7/089
摘要： Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.
摘要翻译：公开了一种用于产生输出信号的内插电路，该输出信号的延迟时间对应于通过以预设的内部分频比执行输入的第一和第二信号之间的相位差的内部分割所获得的值。内插电路包括波形合成单元和偏置控制单元。波形合成单元包括或门，其接收第一和第二信号，以输出这两个信号之间的逻辑或; 第一开关元件，其插入在连接到输出端子的节点和第一电源之间，并且由OR门的输出信号导通和截止; 串联电路，包括由第一信号导通和断开的第一恒流源和第二开关元件; 以及包括由所述第二信号导通和断开的第二恒流源和第三开关元件的串联电路; 串联电路并联连接在输出节点和第二电源之间。基于决定内部分频比的控制信号，偏置控制单元以电流路径开关导通和截止的方式执行控制，使得作为当前值的总和的第一和第二电流值将分别流入第一和第二恒定电流源。

85. 发明授权

US6055196A Semiconductor device with increased replacement efficiency by redundant memory cell arrays 失效
标题翻译：半导体器件通过冗余存储单元阵列提高了替换效率
公开(公告)号：US6055196A
公开(公告)日：2000-04-25
申请号：US84107
申请日：1998-05-26
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/781 , G11C29/808
摘要： A semiconductor memory device is disclosed that allows an increase in the replacement efficiency by redundant memory cell arrays. Redundant row address judging circuits output redundant row selection signals for differing banks, whereby redundant row selection signals are not outputted to other banks in cases in which row addresses of defective memory cells have been programmed to replace the word lines of a particular bank by a redundant memory cell array.
摘要翻译：公开了一种允许通过冗余存储单元阵列提高替换效率的半导体存储器件。冗余行地址判断电路输出用于不同存储体的冗余行选择信号，由此在有缺陷存储器单元的行地址已被编程为用特定存储单元的字线代替冗余的冗余行选择信号的冗余行选择信号存储单元阵列。

86. 发明授权

US5608686A Synchronous semiconductor memory device with low power consumption 失效
标题翻译：具有低功耗的同步半导体存储器件
公开(公告)号：US5608686A
公开(公告)日：1997-03-04
申请号：US512420
申请日：1995-08-08
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C7/1006
摘要： A synchronous semiconductor memory device has an M-bit I/O configuration memory device mode and an M.times.2.sup.k -bit I/O configuration memory device mode. In the former mode, n bits whose transition frequencies are smaller are selected from an m-bit internal address and are used to access a memory section, while the other k (=m-n) bits whose transition frequencies are larger are selected from the m-bit internal address to select one of 2.sup.k groups of internal data lines of the memory section and connect them to some of data input/output pins. In the latter mode, n bits whose transition frequencies are larger are selected from the m-bit internal address and are used to access the memory section, while the 2.sup.k groups of the data lines are connected to all the data input/output pins.
摘要翻译：同步半导体存储器件具有M位I / O配置存储器件模式和Mx2k位I / O配置存储器件模式。在前一种模式中，从m位内部地址中选择转移频率较小的n位，并且用于访问存储器部分，而从m位选择转移频率较大的其他k（= mn）位，位内部地址选择存储器部分的2k组内部数据线之一，并将其连接到某些数据输入/输出引脚。在后一种模式中，从m位内部地址中选择n个过渡频率较大的位，用于访问存储器部分，而2k组数据线连接到所有数据输入/输出引脚。

87. 发明授权

US5539693A Method of controlling semiconductor storage circuit 失效
标题翻译：半导体存储电路的控制方法
公开(公告)号：US5539693A
公开(公告)日：1996-07-23
申请号：US362157
申请日：1994-12-22
申请人： Yasuji Koshikawa , Yasuhiro Takai
发明人： Yasuji Koshikawa , Yasuhiro Takai
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/413 , G11C11/40
CPC分类号： G11C7/1072 , G11C2207/2218
摘要： In the semiconductor integrated circuit of the present invention, write and read operation are successively implemented in which a manner that read addresses are inputted after write addresses are inputted and read data is read from a sense amplifier starting from the next cycle after all the data have been written to the sense amplifier.
摘要翻译：在本发明的半导体集成电路中，依次执行写入和读取操作，其中在写入地址之后输入读取地址的方式被输入，并且从所有数据具有的下一个周期开始从读出放大器读出读取数据被写入感测放大器。

88. 发明授权

US07783220B2 Roller drive control method of fixing apparatus and fixing apparatus 有权
标题翻译：定影装置和定影装置的滚筒驱动控制方法
公开(公告)号：US07783220B2
公开(公告)日：2010-08-24
申请号：US11839621
申请日：2007-08-16
申请人： Yoshinobu Tateishi , Yasuhiro Takai
发明人： Yoshinobu Tateishi , Yasuhiro Takai
IPC分类号： G03G15/20
CPC分类号： G03G15/2025 , G03G15/2028
摘要： In one embodiment, a predetermined period different from a fixing process period in which fixing of toner to recording paper is carried out is set as a toner removal period, and during the toner removal period a hot roller and a pressure roller are intermittently rotated, and separation claws in contact with the rollers are caused to vibrate by the intermittent rotation of the rollers such that toner adhered to the separation claws is caused to drop due to this and is removed. Also, faces of the separation claws that oppose the surfaces of the hot roller and the pressure roller are set in a convex shape.
摘要翻译：在一个实施例中，与执行调色剂到记录纸的定影的定影处理周期不同的预定时段被设置为调色剂去除时段，并且在调色剂移除期间，热辊和加压辊间歇地旋转，与辊接触的分离爪通过辊的间歇旋转而振动，使得附着在分离爪上的调色剂由此而下降，并被除去。此外，与热辊和加压辊的表面相对的分离爪的面被设定为凸形。

89. 发明授权

US07750712B2 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US07750712B2
公开(公告)日：2010-07-06
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

90. 发明授权

US07719370B2 Voltage controlled oscillator 有权
标题翻译：压控振荡器
公开(公告)号：US07719370B2
公开(公告)日：2010-05-18
申请号：US12031809
申请日：2008-02-15
申请人： Yasuhiro Takai
发明人： Yasuhiro Takai
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K5/133 , H03L7/0995
摘要： A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.
摘要翻译：一种压控振荡器，其是差分环形振荡器型压控振荡器，其通过连接到级联差分延迟元件中，相位反相的差分时钟信号被输入到差分延迟元件中，并且通过偏置电压来控制流向差分延迟元件的电流控制该差分时钟信号的延迟量，具有相位检测部分，该相位检测部分通过比较任何差分延迟元件的差分输出的输出电压和设置为检测异常运算的电压的参考电压来输出检测信号以及设置在每个差分延迟元件处的交叉耦合电路，并且当输入检测信号时，放大该对差分输出端子之间的电位差。

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