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81. 发明申请

US20060252226A1 Integrated SOI fingered decoupling capacitor 失效
公开(公告)号：US20060252226A1
公开(公告)日：2006-11-09
申请号：US11485599
申请日：2006-07-12
申请人： Zarchary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
发明人： Zarchary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： H01L21/76
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1087 , H01L27/1203
摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

82. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

83. 发明申请

US20060128071A1 Integrated antifuse structure for finfet and cmos devices 有权
标题翻译： Finf集成反熔丝结构和cmos器件
公开(公告)号：US20060128071A1
公开(公告)日：2006-06-15
申请号：US10539333
申请日：2002-12-20
申请人： Jed Rankin , Wagdl Abadeer , Jeffrey Brown , William Tonti
发明人： Jed Rankin , Wagdl Abadeer , Jeffrey Brown , William Tonti
IPC分类号： H01L21/82
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/785
摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).
摘要翻译：描述了与半导体器件（例如FINFET或平面CMOS器件）集成的制造和反熔丝结构（100）的方法。设置在设置在基板（10）上的绝缘体（3）上的半导体材料（11）的区域; 蚀刻工艺暴露了半导体材料中的多个拐角（111-114）。露出的角部被氧化，以形成角落处的细长尖端（111t-114t）; 去除顶部上方的氧化物（31）。然后在半导体材料上形成氧化物层（例如栅极氧化物），并覆盖在角部上; 该层在拐角处具有减小的厚度。在角部处形成与氧化物层（51）接触的导电材料层（60），从而通过氧化物层在半导体材料和导电材料层之间形成多个可能的击穿路径。将诸如老化电压的电压施加到结构将至少一个击穿路径转换成导电路径（103,280）。

84. 发明申请

US20050151213A1 METHOD AND STRUCTURE FOR INTEGRATING THERMISTOR 失效
标题翻译：集成热敏电阻的方法和结构
公开(公告)号：US20050151213A1
公开(公告)日：2005-07-14
申请号：US10707746
申请日：2004-01-08
申请人： Jon Casey , William Ferrante , Edward Kiewra , Carl Radens , William Tonti
发明人： Jon Casey , William Ferrante , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： H01L21/28 , G01K7/22 , H01C7/00 , H01L21/3205 , H01L21/762 , H01L21/768 , H01L21/822 , H01L23/52 , H01L27/04 , H01L21/00 , H01L27/14 , H01L29/82 , H01L31/058
CPC分类号： H01L21/76895 , G01K7/226 , H01C7/006 , H01L21/76224 , H01L21/76838
摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).
摘要翻译：提供了用于形成热敏电阻的结构和方法。隔离结构形成在至少包括单晶半导体的上层的基板中。一层自杀化合物前体沉积在隔离区和上层上。然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

85. 发明申请

US20050133884A1 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US20050133884A1
公开(公告)日：2005-06-23
申请号：US11051703
申请日：2005-02-04
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

86. 发明申请

US20050125707A1 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US20050125707A1
公开(公告)日：2005-06-09
申请号：US10729751
申请日：2003-12-04
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

87. 发明申请

US20050122160A1 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US20050122160A1
公开(公告)日：2005-06-09
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
发明人： Wagdi Abadeer , Jennifer Appleyard , John Fifield , William Tonti
IPC分类号： G05F3/02 , G05F3/24
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

88. 发明申请

US20050051868A1 Method of closing an antifuse 失效
标题翻译：关闭反熔丝的方法
公开(公告)号：US20050051868A1
公开(公告)日：2005-03-10
申请号：US10971238
申请日：2004-10-22
申请人： William Motsiff , William Tonti , Richard Williams
发明人： William Motsiff , William Tonti , Richard Williams
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译：一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。脉冲激光能量软化金属片段，静电场使金属片段彼此接触。静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

89. 发明申请

US20070292996A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
标题翻译：加工薄膜和薄膜的方法和结构以及可变的熔化到熔融间隙
公开(公告)号：US20070292996A1
公开(公告)日：2007-12-20
申请号：US11846544
申请日：2007-08-29
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthler , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthler , Jed Rankin , William Tonti
IPC分类号： H01L21/84
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.
摘要翻译：公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

90. 发明授权

US07190046B2 Bipolar transistor having reduced collector-base capacitance 失效
标题翻译：双极晶体管具有降低的集电极 - 基极电容
公开(公告)号：US07190046B2
公开(公告)日：2007-03-13
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

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